公开(公告)号：US12131065B2

公开(公告)日：2024-10-29

申请号：US17407015

申请日：2021-08-19

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Benjamin Rivera ,  Joseph A. De La Cerda ,  Bruce J. Ford ,  Nicolas Soberanes

IPC: G06F3/06 ,  G06N3/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/067 ,  G06N3/04

Abstract: Apparatuses and methods can be related to reducing memory device overhead using artificial intelligence (AI). Reducing overhead can include receiving file metadata of a data file and device metadata of the memory device. Based on the file metadata and the device metadata, a number of indicators can be selected to provide an indication of an expected use of the data file in the memory device. The number of indicators can be provided to the memory device. The data file can be stored with different data files having matching indicators corresponding thereto.

公开(公告)号：US20230057577A1

公开(公告)日：2023-02-23

申请号：US17406896

申请日：2021-08-19

Applicant: Micron Technology, Inc.

Inventor： Joseph A. De La Cerda ,  Bruce J. Ford ,  Benjamin Rivera ,  Nicolas Soberanes

IPC: G06F12/02 ,  G06F3/06 ,  G06K9/62 ,  G06N3/04

Abstract: Apparatuses and methods can be related to performing prediction based garbage collection. Performing prediction based garbage collection can include performing a first instance of garbage collection, of the memory device, using a first circuitry of the controller and generating a prediction using a second circuitry of the controller. A confidence interval can also be generated for the prediction using the second circuitry of the controller. Responsive to determining that the confidence interval is greater than a threshold, a second instance of garbage collection, of the memory device, can be triggered using the first circuitry of the controller where the first instance of garbage collection is triggered before the second instance of garbage collection.

公开(公告)号：US20210389908A1

公开(公告)日：2021-12-16

申请号：US16902845

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Benjamin Rivera ,  Nicolas Soberanes ,  Avani F. Trivedi ,  Joseph A. De La Cerda ,  Bruce J. Ford

IPC: G06F3/06 ,  G06F11/07

Abstract: Methods, systems, and devices for adjustable media management are described. A media management operation may be performed at a first rate. During the media management operation, invalid data may be moved from a first block of memory cells to a second block of memory cells at the first rate to free space in the first block. Based on one or more conditions of the memory device, the rate that the media management operation is performed may be adjusted to a second rate. For example, the rate may be lowered based on a quantity of access operations performed on the memory device. Invalid data may continue to be moved from the first block of memory cells to the second block of memory cells at the second rate.

公开(公告)号：US11698858B2

公开(公告)日：2023-07-11

申请号：US17406896

申请日：2021-08-19

Applicant: Micron Technology, Inc.

Inventor： Joseph A. De La Cerda ,  Bruce J. Ford ,  Benjamin Rivera ,  Nicolas Soberanes

IPC: G06F3/06 ,  G06F12/02 ,  G06N3/04 ,  G06F18/214

CPC classification number: G06F12/0253 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F18/214 ,  G06N3/04

Abstract: Apparatuses and methods can be related to performing prediction based garbage collection. Performing prediction based garbage collection can include performing a first instance of garbage collection, of the memory device, using a first circuitry of the controller and generating a prediction using a second circuitry of the controller. A confidence interval can also be generated for the prediction using the second circuitry of the controller. Responsive to determining that the confidence interval is greater than a threshold, a second instance of garbage collection, of the memory device, can be triggered using the first circuitry of the controller where the first instance of garbage collection is triggered before the second instance of garbage collection.

公开(公告)号：US11521694B2

公开(公告)日：2022-12-06

申请号：US17307798

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Joseph A. De La Cerda ,  Benjamin Rivera ,  Bruce J. Ford ,  Nicolas Soberanes ,  Christopher Moore

IPC: G11C7/04 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44

Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

公开(公告)号：US11989421B2

公开(公告)日：2024-05-21

申请号：US17406997

申请日：2021-08-19

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Nicolas Soberanes ,  Joseph A. De La Cerda ,  Benjamin Rivera ,  Bruce J. Ford

IPC: G06F3/06 ,  G06F21/62

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F21/6218

Abstract: Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.

公开(公告)号：US11880595B2

公开(公告)日：2024-01-23

申请号：US17091980

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Nicolas Soberanes ,  Joseph A. De La Cerda ,  Benjamin Rivera ,  Bruce J. Ford

IPC: G06F3/06 ,  G06N20/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06N20/00

Abstract: Methods, systems, and devices for memory cell access techniques for memory systems are described. A memory system may receive, from a host system, a set of commands to write data to the memory system. The memory system may analyze a set of parameters associated with the set of commands based on receiving the set of commands. The memory system may determine whether to write the data of the set of commands to the memory system using a first mode or a second mode based on analyzing the parameters. The memory system may write the data using the first mode or the second mode based on the determining.

公开(公告)号：US11869611B2

公开(公告)日：2024-01-09

申请号：US18074228

申请日：2022-12-02

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Joseph A. De La Cerda ,  Benjamin Rivera ,  Bruce J. Ford ,  Nicolas Soberanes ,  Christopher Moore

IPC: G11C7/04 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/028 ,  G11C7/04 ,  G11C29/12015 ,  G11C29/44

Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

公开(公告)号：US12147702B2

公开(公告)日：2024-11-19

申请号：US17579995

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Nicolas Soberanes ,  Ezra E. Hartz ,  Jonathan S. Parry ,  Bruce J. Ford ,  Joseph A. De La Cerda ,  Benjamin Rivera

IPC: G06F3/06 ,  G06F12/0811 ,  G06F18/214

Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

公开(公告)号：US11715511B2

公开(公告)日：2023-08-01

申请号：US17558099

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Joseph A. De La Cerda ,  Nicolas Soberanes ,  Christopher Moore ,  Bruce J. Ford ,  Benjamin Rivera

IPC: G11C11/406 ,  G11C11/54 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/4096 ,  G11C11/40615 ,  G11C11/54 ,  G11C2211/4062

Abstract: A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.