-
公开(公告)号：US11994942B2
公开(公告)日：2024-05-28
申请号：US17558035
申请日：2021-12-21
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Nicolas Soberanes , Christopher Moore , Bruce J. Ford , Benjamin Rivera
CPC classification number: G06F11/0793 , G06F11/0727 , G06F11/076
Abstract: A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.
-
公开(公告)号：US20230197137A1
公开(公告)日：2023-06-22
申请号：US17558099
申请日：2021-12-21
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Nicolas Soberanes , Christopher Moore , Bruce J. Ford , Benjamin Rivera
IPC: G11C11/406 , G11C11/4096 , G11C11/54
CPC classification number: G11C11/40622 , G11C11/40615 , G11C11/4096 , G11C11/54 , G11C2211/4062
Abstract: A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.
-
公开(公告)号：US20230095397A1
公开(公告)日：2023-03-30
申请号：US18074228
申请日：2022-12-02
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Benjamin Rivera , Bruce J. Ford , Nicolas Soberanes , Christopher Moore
Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.
-
Patent Agency Ranking
公开(公告)号：US11715511B2
公开(公告)日：2023-08-01
申请号：US17558099
申请日：2021-12-21
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Nicolas Soberanes , Christopher Moore , Bruce J. Ford , Benjamin Rivera
IPC: G11C11/406 , G11C11/54 , G11C11/4096
CPC classification number: G11C11/40622 , G11C11/4096 , G11C11/40615 , G11C11/54 , G11C2211/4062
Abstract: A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.
-
公开(公告)号：US20230195559A1
公开(公告)日：2023-06-22
申请号：US17558035
申请日：2021-12-21
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Nicolas Soberanes , Christopher Moore , Bruce J. Ford , Benjamin Rivera
IPC: G06F11/07
CPC classification number: G06F11/0793 , G06F11/0727 , G06F11/076
Abstract: A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.
-
公开(公告)号：US20220359028A1
公开(公告)日：2022-11-10
申请号：US17307798
申请日：2021-05-04
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Benjamin Rivera , Bruce J. Ford , Nicolas Soberanes , Christopher Moore
Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.
-
公开(公告)号：US11869611B2
公开(公告)日：2024-01-09
申请号：US18074228
申请日：2022-12-02
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Benjamin Rivera , Bruce J. Ford , Nicolas Soberanes , Christopher Moore
CPC classification number: G11C29/028 , G11C7/04 , G11C29/12015 , G11C29/44
Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.
-
公开(公告)号：US11521694B2
公开(公告)日：2022-12-06
申请号：US17307798
申请日：2021-05-04
Applicant: Micron Technology, Inc.
Inventor： Ezra E. Hartz , Joseph A. De La Cerda , Benjamin Rivera , Bruce J. Ford , Nicolas Soberanes , Christopher Moore
Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.016 seconds)
