公开(公告)号：US11409674B2

公开(公告)日：2022-08-09

申请号：US17062484

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/406 ,  G11C11/4096

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US20230029003A1

公开(公告)日：2023-01-26

申请号：US17949836

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Vaughn N. Johnson ,  Debra M. Bell ,  Miles S. Wiscombe ,  Brian T. Pecha ,  Kyle Alexander

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

公开(公告)号：US20220172771A1

公开(公告)日：2022-06-02

申请号：US17107306

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Debra M. Bell ,  Brian T. Pecha ,  Vaughn N. Johnson ,  Kyle Alexander

IPC: G11C11/406 ,  G11C11/408

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to conditionally activate certain rows during refresh operations such that the memory devices can execute operations directed to the activated rows concurrently with the refresh operations. In some embodiments, the memory device receives an activate (ACT) command directed to a section of a memory bank while performing refresh operations for the memory bank. The memory device may carry out the ACT command if certain conditions are satisfied not to corrupt the data being refreshed. Subsequently, the memory device generates a signal to indicate the ACT command has been accepted to activate a row identified by the ACT command. Further, the memory device can perform subsequent access commands directed to the row, in parallel with the refresh operations.

公开(公告)号：US20220391334A1

公开(公告)日：2022-12-08

申请号：US17882550

申请日：2022-08-06

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/406 ,  G11C11/4096

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US11468939B2

公开(公告)日：2022-10-11

申请号：US17107306

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Debra M. Bell ,  Brian T. Pecha ,  Vaughn N. Johnson ,  Kyle Alexander

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to conditionally activate certain rows during refresh operations such that the memory devices can execute operations directed to the activated rows concurrently with the refresh operations. In some embodiments, the memory device receives an activate (ACT) command directed to a section of a memory bank while performing refresh operations for the memory bank. The memory device may carry out the ACT command if certain conditions are satisfied not to corrupt the data being refreshed. Subsequently, the memory device generates a signal to indicate the ACT command has been accepted to activate a row identified by the ACT command. Further, the memory device can perform subsequent access commands directed to the row, in parallel with the refresh operations.

公开(公告)号：US11468938B2

公开(公告)日：2022-10-11

申请号：US17096469

申请日：2020-11-12

Applicant: Micron Technology, Inc.

Inventor： Vaughn N. Johnson ,  Debra M. Bell ,  Miles S. Wiscombe ,  Brian T. Pecha ,  Kyle Alexander

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

公开(公告)号：US20220148647A1

公开(公告)日：2022-05-12

申请号：US17096469

申请日：2020-11-12

Applicant: Micron Technology, Inc.

Inventor： Vaughn N. Johnson ,  Debra M. Bell ,  Miles S. Wiscombe ,  Brian T. Pecha ,  Kyle Alexander

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

公开(公告)号：US20220107905A1

公开(公告)日：2022-04-07

申请号：US17062484

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/4096 ,  G11C11/406

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.