公开(公告)号：US20250060909A1

公开(公告)日：2025-02-20

申请号：US18933047

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Roy Leonard ,  Xiaolei Man ,  Bryan Li ,  Peijing Ye

IPC: G06F3/06 ,  G06F12/0811

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the cache. The cache has a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

公开(公告)号：US12182452B2

公开(公告)日：2024-12-31

申请号：US18503275

申请日：2023-11-07

Applicant: Micron Technology, Inc.

Inventor： Roy Leonard ,  Xiaolei Man ,  Bryan Li ,  Peijing Ye

IPC: G06F3/06 ,  G06F12/0811

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

公开(公告)号：US20240078047A1

公开(公告)日：2024-03-07

申请号：US18503275

申请日：2023-11-07

Applicant: Micron Technology, Inc.

Inventor： Roy Leonard ,  Xiaolei Man ,  Bryan Li ,  Peijing Ye

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0679 ,  G06F12/0811

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

公开(公告)号：US20230297279A1

公开(公告)日：2023-09-21

申请号：US17698182

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Roy Leonard ,  Xiaolei Man ,  Bryan Li ,  Peijing Ye

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0659 ,  G06F3/0635 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0811

Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.

公开(公告)号：US11861234B2

公开(公告)日：2024-01-02

申请号：US17698182

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Roy Leonard ,  Xiaolei Man ,  Bryan Li ,  Peijing Ye

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0679 ,  G06F12/0811

Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.