-
公开(公告)号：US20250060909A1
公开(公告)日：2025-02-20
申请号：US18933047
申请日：2024-10-31
Applicant: Micron Technology, Inc.
Inventor： Roy Leonard , Xiaolei Man , Bryan Li , Peijing Ye
IPC: G06F3/06 , G06F12/0811
Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the cache. The cache has a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
-
公开(公告)号：US11861234B2
公开(公告)日：2024-01-02
申请号：US17698182
申请日：2022-03-18
Applicant: Micron Technology, Inc.
Inventor： Roy Leonard , Xiaolei Man , Bryan Li , Peijing Ye
IPC: G06F3/06 , G06F12/0811
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0635 , G06F3/0679 , G06F12/0811
Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.
-
公开(公告)号：US12223208B2
公开(公告)日：2025-02-11
申请号：US18513742
申请日：2023-11-20
Applicant: Micron Technology, Inc.
Inventor： Daniel J. Hubbard , Roy Leonard
IPC: G06F3/06 , G06F12/0846 , G06F12/0882
Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.
-
公开(公告)号：US20230342081A1
公开(公告)日：2023-10-26
申请号：US17727131
申请日：2022-04-22
Applicant: Micron Technology, Inc.
Inventor： Daniel J. Hubbard , Roy Leonard
IPC: G06F12/0882 , G06F3/06 , G06F12/0846
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0851 , G06F12/0882
Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.
-
公开(公告)号：US20230268018A1
公开(公告)日：2023-08-24
申请号：US17675477
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Vamsi Rayaprolu , Ashutosh Malshe , Gary Besinga , Roy Leonard
CPC classification number: G11C16/3495 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/32
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.
-
Patent Agency Ranking
公开(公告)号：US12182452B2
公开(公告)日：2024-12-31
申请号：US18503275
申请日：2023-11-07
Applicant: Micron Technology, Inc.
Inventor： Roy Leonard , Xiaolei Man , Bryan Li , Peijing Ye
IPC: G06F3/06 , G06F12/0811
Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
-
公开(公告)号：US20240078047A1
公开(公告)日：2024-03-07
申请号：US18503275
申请日：2023-11-07
Applicant: Micron Technology, Inc.
Inventor： Roy Leonard , Xiaolei Man , Bryan Li , Peijing Ye
IPC: G06F3/06 , G06F12/0811
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0635 , G06F3/0679 , G06F12/0811
Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
-
公开(公告)号：US11875061B2
公开(公告)日：2024-01-16
申请号：US17727131
申请日：2022-04-22
Applicant: Micron Technology, Inc.
Inventor： Daniel J. Hubbard , Roy Leonard
IPC: G06F3/06 , G06F12/0882 , G06F12/0846
CPC classification number: G06F3/0659 , G06F3/064 , G06F3/0604 , G06F3/0679 , G06F12/0851 , G06F12/0882
Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.
-
公开(公告)号：US12272412B2
公开(公告)日：2025-04-08
申请号：US18394660
申请日：2023-12-22
Applicant: Micron Technology, Inc.
Inventor： Vamsi Rayaprolu , Ashutosh Malshe , Gary Besinga , Roy Leonard
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
-
公开(公告)号：US20240127900A1
公开(公告)日：2024-04-18
申请号：US18394660
申请日：2023-12-22
Applicant: Micron Technology, Inc.
Inventor： Vamsi Rayaprolu , Ashutosh Malshe , Gary Besinga , Roy Leonard
CPC classification number: G11C16/3495 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/32
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.019 seconds)
