公开(公告)号：US20220019533A1

公开(公告)日：2022-01-20

申请号：US16928999

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Cagdas Dirik, II ,  Laurent Isenegger ,  Robert M. Walker

IPC: G06F12/0806

Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.