公开(公告)号：US20240184596A1

公开(公告)日：2024-06-06

申请号：US17904081

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Jiawei Wang ,  Zephyr Yu ,  Yaming Lu ,  Long Lu ,  Huachen Li ,  Wenjun Wu ,  Chen Huang

IPC: G06F9/30

CPC classification number: G06F9/30178

Abstract: Methods, systems, and devices for compressing firmware data are described. A memory system may access firmware data associated with the memory system that includes bank data. The memory system may determine whether the bank data in the firmware data is compressed and, in cases that the bank data is compressed, the memory system may decompress the bank data prior to storing the bank data at a controller of the memory system. In some examples, a bank header in the firmware data may include information for the memory system to decompress the bank data. For example, the bank header may indicate the size of the compressed bank data associated with each bank. Additionally, the memory system may read the compressed bank data according to the indicated size and store the bank data at the controller or at a memory device of the memory system.

公开(公告)号：US20240345759A1

公开(公告)日：2024-10-17

申请号：US18646025

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Zhou Zhou ,  Chaofeng Zhang ,  Jianfeng Li ,  Chen Huang ,  Lin Huang ,  Wei Li

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for improved implicit ordered command handling are described. For instance, a memory device may receive, from a host device, a first command and a second command. The memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. The memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.

公开(公告)号：US11995337B2

公开(公告)日：2024-05-28

申请号：US17283210

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Zhou Zhou ,  Chaofeng Zhang ,  Jianfeng Li ,  Chen Huang ,  Lin Huang ,  Wei Li

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for improved implicit ordered command handling are described. For instance, a memory device may receive, from a host device, a first command and a second command. The memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. The memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.