公开(公告)号：US20150134898A1

公开(公告)日：2015-05-14

申请号：US14599892

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G11C7/10 ,  G06F12/06

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract translation: 提供了系统和方法来管理对寄存器的访问。 在一个实施例中，系统可以包括处理器和多个寄存器。 处理器和多个寄存器可以集成到单个设备中，或者可以在单独的设备中。 多个寄存器可以包括可由处理器直接访问的第一组寄存器和不能由处理器直接访问的第二组寄存器。 然而，第二组寄存器可以由处理器经由第一组寄存器间接访问。 在一个实施例中，第一组寄存器可以包括用于从第二组寄存器中选择寄存器组的寄存器和用于选择寄存器组中的特定地址的寄存器，以允许处理器间接访问寄存器组的寄存器 第二集

公开(公告)号：US09734876B2

公开(公告)日：2017-08-15

申请号：US14599892

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/30 ,  G06F9/34 ,  G06F12/06

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

公开(公告)号：US10020033B2

公开(公告)日：2018-07-10

申请号：US15676796

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/30 ,  G06F9/34 ,  G06F12/06

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

公开(公告)号：US20170345467A1

公开(公告)日：2017-11-30

申请号：US15676796

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G11C7/10 ,  G06F12/06 ,  G06F9/30 ,  G06F9/34

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.