公开(公告)号：US12148483B2

公开(公告)日：2024-11-19

申请号：US18539798

申请日：2023-12-14

Applicant: Micron Technology, Inc.

Inventor： Agostino Macerola ,  Gianni Rea

IPC: G11C7/04 ,  G11C16/04 ,  G11C16/32 ,  H03M1/10 ,  H03H11/24

Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.

公开(公告)号：US20230111614A1

公开(公告)日：2023-04-13

申请号：US17684956

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Agostino Macerola ,  Gianni Rea

IPC: G11C16/32 ,  G11C16/04 ,  H03M1/10

Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.

公开(公告)号：US20240120012A1

公开(公告)日：2024-04-11

申请号：US18539798

申请日：2023-12-14

Applicant: Micron Technology, Inc.

Inventor： Agostino Macerola ,  Gianni Rea

IPC: G11C16/32 ,  G11C7/04 ,  G11C16/04 ,  H03M1/10

CPC classification number: G11C16/32 ,  G11C7/04 ,  G11C16/0483 ,  H03M1/1009 ,  H03H11/245

Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.

公开(公告)号：US11908530B2

公开(公告)日：2024-02-20

申请号：US17684956

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Agostino Macerola ,  Gianni Rea

IPC: G11C7/04 ,  G11C16/32 ,  H03M1/10 ,  G11C16/04 ,  H03H11/24

CPC classification number: G11C16/32 ,  G11C7/04 ,  G11C16/0483 ,  H03M1/1009 ,  H03H11/245

Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.