公开(公告)号：US11721379B2

公开(公告)日：2023-08-08

申请号：US17350771

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir J. Javanifard

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage or a third voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage or the third voltage. In some instances, the digit lines may be selected (e.g., driven) according to a pattern.

公开(公告)号：US11670357B2

公开(公告)日：2023-06-06

申请号：US17350757

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir J. Javanifard

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4072 ,  G11C11/22

CPC classification number: G11C11/4074 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2297 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4096

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

公开(公告)号：US20220406356A1

公开(公告)日：2022-12-22

申请号：US17350757

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir J. Javanifard

IPC: G11C11/4074 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4096

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

公开(公告)号：US20220406355A1

公开(公告)日：2022-12-22

申请号：US17350771

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir J. Javanifard

IPC: G11C11/22

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage or a third voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage or the third voltage. In some instances, the digit lines may be selected (e.g., driven) according to a pattern.