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    FERROELECTRIC MEMORY DEVICE WITH MULTI-LEVEL BIT CELL
    3.
    发明公开
    FERROELECTRIC MEMORY DEVICE WITH MULTI-LEVEL BIT CELL 审中-公开

    公开(公告)号：US20240284680A1

    公开(公告)日：2024-08-22

    申请号：US18172027

    申请日：2023-02-21

    申请人： GlobalFoundries U.S. Inc.

    发明人： Zhixing Zhao ,  Dominik M. Kleimaier ,  Stefan Duenkel

    IPC分类号： H10B51/30 ,  G11C11/22 ,  H01L29/78

    CPC分类号： H10B51/30 ,  G11C11/2275 ,  H01L29/78391

    摘要： A ferroelectric memory device includes a substrate including a source region and a drain region, and a gate structure disposed over the substrate. The gate structure includes a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate, an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, and a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.

    Unbalanced programmed data states in memory
    4.
    发明授权
    Unbalanced programmed data states in memory 有权

    公开(公告)号：US12068016B2

    公开(公告)日：2024-08-20

    申请号：US17712948

    申请日：2022-04-04

    申请人： Micron Technology, Inc.

    发明人： Christophe Laurent ,  Riccardo Muzzetto

    IPC分类号： G11C11/22 ,  G11C7/10 ,  G11C16/34

    CPC分类号： G11C11/2275 ,  G11C7/1006 ,  G11C11/221 ,  G11C11/2273 ,  G11C16/34

    摘要： The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

    Ferroelectric memory cell access
    5.
    发明授权
    Ferroelectric memory cell access 有权

    公开(公告)号：US12062389B2

    公开(公告)日：2024-08-13

    申请号：US17323968

    申请日：2021-05-18

    申请人： Micron Technology, Inc.

    发明人： Umberto Di Vincenzo

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2259 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

    摘要： Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

    DEVICES, METHODS, AND SYSTEMS FOR CALIBRATING A READ VOLTAGE USED FOR READING MEMORY CELLS
    6.
    发明公开
    DEVICES, METHODS, AND SYSTEMS FOR CALIBRATING A READ VOLTAGE USED FOR READING MEMORY CELLS 审中-公开

    公开(公告)号：US20240265959A1

    公开(公告)日：2024-08-08

    申请号：US18106872

    申请日：2023-02-07

    申请人： Ferroelectric Memory GmbH

    发明人： Stefano Sivero ,  Alessandro Palludo

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2275

    摘要： Disclosed herein are devices, methods, and systems for calibrating a read voltage level for reading memory cells of a memory. The calibration circuit includes a reference cell associated with a predefined programming state of the reference cell. The calibration circuit also includes a read circuit configured to (e.g., until a read state of the reference cell matches the predefined programming state), perform a read operation on the reference cell at a reference read voltage level to obtain a read state of the reference cell and adjust the reference read voltage level to an adjusted reference read voltage level based on a comparison between the read state and the predefined programming state. The read circuit is configured to provide the adjusted reference read voltage level to the memory as the read voltage level for reading the memory cells of the memory.