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公开(公告)号：US20210134364A1
公开(公告)日：2021-05-06
申请号：US17037495
申请日：2020-09-29
Applicant: Micron Technology, Inc.
Inventor： Mingdong Cui , Nathan Joseph Sirocka , Byung Sick Moon , Jeffrey Edward Koelling
IPC: G11C13/00
Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and −4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and −4.5V.
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Patent Agency Ranking
公开(公告)号：US11605425B2
公开(公告)日：2023-03-14
申请号：US17350422
申请日：2021-06-17
Applicant: Micron Technology, Inc.
Inventor： Nathan Joseph Sirocka , Mingdong Cui , Jeffrey Edward Koelling
Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative section are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.
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公开(公告)号：US11074970B2
公开(公告)日：2021-07-27
申请号：US16668549
申请日：2019-10-30
Applicant: Micron Technology, Inc.
Inventor： Nathan Joseph Sirocka , Mingdong Cui , Jeffrey Edward Koelling
Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.
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公开(公告)号：US11183237B2
公开(公告)日：2021-11-23
申请号：US17037495
申请日：2020-09-29
Applicant: Micron Technology, Inc.
Inventor： Mingdong Cui , Nathan Joseph Sirocka , Byung Sick Moon , Jeffrey Edward Koelling
Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and −4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and −4.5V.
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公开(公告)号：US20210312981A1
公开(公告)日：2021-10-07
申请号：US17350422
申请日：2021-06-17
Applicant: Micron Technology, Inc.
Inventor： Nathan Joseph Sirocka , Mingdong Cui , Jeffrey Edward Koelling
IPC: G11C13/00
Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.
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公开(公告)号：US20210134363A1
公开(公告)日：2021-05-06
申请号：US16668549
申请日：2019-10-30
Applicant: Micron Technology, Inc.
Inventor： Nathan Joseph Sirocka , Mingdong Cui , Jeffrey Edward Koelling
IPC: G11C13/00
Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.
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