公开(公告)号：US20240201893A1

公开(公告)日：2024-06-20

申请号：US18541846

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Sumit Tayal ,  Joseph A. Oberle ,  David C. Sastry ,  Anil Kumar Agarwal

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: A method includes performing a self-initiated test memory operation of a memory device in a memory sub-system and detecting, via a sensor circuit, an input voltage or input current of the memory device or the memory sub-system. The method further includes determining whether the input voltage or the input current meets a degradation criteria and generating a management control signal responsive based on the determination whether the input voltage or the input current meets the degradation criteria.

公开(公告)号：US20240330174A1

公开(公告)日：2024-10-03

申请号：US18608251

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Shawn Storm ,  Joseph A. Oberle ,  Ji-Hye Gale Shin

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A method includes configuring a memory system with a first set of operating characteristics corresponding to a first thermal voltage model, monitoring operation of the memory system, selecting a second thermal voltage model based on the monitored operation of the memory system, configuring the memory system with a second set of operating characteristics corresponding to the second thermal voltage model, and writing data to the memory system configured with the second set of operating characteristics.

公开(公告)号：US20240201891A1

公开(公告)日：2024-06-20

申请号：US18539161

申请日：2023-12-13

Applicant: Micron Technology, Inc.

Inventor： Joseph A. Oberle ,  David C. Sastry ,  Anil Kumar Agarwal ,  Sumit Tayal

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method includes performing a host-initiated test memory operation of a memory device in a memory sub-system and detecting, via a sensor circuit, an input voltage or input current of the memory device or the memory sub-system. The method further includes determining whether the input voltage or the input current meets a degradation criteria and generating a management control signal responsive based on the determination whether the input voltage or the input current meets the degradation criteria.