公开(公告)号：US20230393752A1

公开(公告)日：2023-12-07

申请号：US17887244

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Nagendra Prasad Ganesh Rao ,  Joshua C. Garrison ,  Jian Huang

IPC: G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G11C16/34 ,  G11C16/0483

Abstract: An example system can include a memory component and a processing device. The memory component can include a group of memory cells. The processing device can be coupled to the memory component. The processing device can be configured to use a first voltage window for a set of memory cells of the group of memory cells during a first time period. The processing device can be configured to determine that an error rate of a sub-set of the set of memory cells is above a threshold error rate. The processing device can be configured to, in response to the determination that the error rate of the sub-set of memory cells is above the threshold error rate, use a second voltage window for the set of memory cells of the group of memory cells during a second time period.