公开(公告)号：US11211347B2

公开(公告)日：2021-12-28

申请号：US17060313

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L23/00 ,  G03F1/54

Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed.

公开(公告)号：US20190355631A1

公开(公告)日：2019-11-21

申请号：US15981619

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L21/66 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad. The insulator material has a minimum elevational thickness from the conductive-test-pad uppermost surface to an uppermost surface of the insulator material that is immediately-adjacent the insulator-material opening and that is less than said minimum elevational thickness of the insulating material. Methods are disclosed.

公开(公告)号：US20190355682A1

公开(公告)日：2019-11-21

申请号：US15981599

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L23/00 ,  G03F1/54

Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed.

公开(公告)号：US10943841B2

公开(公告)日：2021-03-09

申请号：US16830734

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/532 ,  H01L23/528

Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad. The insulator material has a minimum elevational thickness from the conductive-test-pad uppermost surface to an uppermost surface of the insulator material that is immediately-adjacent the insulator-material opening and that is less than said minimum elevational thickness of the insulating material. Methods are disclosed.

公开(公告)号：US20210020592A1

公开(公告)日：2021-01-21

申请号：US17060313

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L23/00 ,  G03F1/54

Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed.

公开(公告)号：US20200227327A1

公开(公告)日：2020-07-16

申请号：US16830734

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L21/66 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad. The insulator material has a minimum elevational thickness from the conductive-test-pad uppermost surface to an uppermost surface of the insulator material that is immediately-adjacent the insulator-material opening and that is less than said minimum elevational thickness of the insulating material. Methods are disclosed.

公开(公告)号：US10651100B2

公开(公告)日：2020-05-12

申请号：US15981619

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

IPC: H01L23/528 ,  H01L21/66 ,  H01L23/532 ,  H01L21/768

Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad. The insulator material has a minimum elevational thickness from the conductive-test-pad uppermost surface to an uppermost surface of the insulator material that is immediately-adjacent the insulator-material opening and that is less than said minimum elevational thickness of the insulating material. Methods are disclosed.