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    SYSTEMS AND METHODS FOR MITIGATING CRACK MEANDERING IN SEMICONDUCTOR DICING
    1.
    发明申请
    SYSTEMS AND METHODS FOR MITIGATING CRACK MEANDERING IN SEMICONDUCTOR DICING 有权

    公开(公告)号：US20250069952A1

    公开(公告)日：2025-02-27

    申请号：US18788846

    申请日：2024-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Vibhav Gupta ,  Wei Chang Mendoza Wong ,  Xinyun Chen ,  Raj K. Bansal ,  Teng Leong Tan

    IPC: H01L21/78 ,  H01L23/00

    Abstract: Systems and methods for mitigating crack meandering, are disclosed herein. In some embodiments, the method includes forming a metallic layer over planned scribe regions of an upper surface of a wafer, then selectively patterning and/or etching the metallic layer to form a plurality of isolated lines over the planned scribe regions. The method can then include depositing a passivation material over the plurality of isolated lines. Adjacent isolated lines can be separated from each other by a small enough distance to disrupt the deposition process, thereby creating a gap in the passivation material between each of the adjacent isolated lines. The gaps and/or trenches formed in the top surface of the wafer by etching the passivation material through the gaps can help attract cracks during a stealth dicing process, thereby reducing the amount the cracks meander away from the planned scribe regions.

    Integrated circuit structures and methods of forming an opening in a material
    2.
    发明授权
    Integrated circuit structures and methods of forming an opening in a material 有权

    公开(公告)号：US11211347B2

    公开(公告)日：2021-12-28

    申请号：US17060313

    申请日：2020-10-01

    Applicant: Micron Technology, Inc.

    Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

    IPC: H01L23/00 ,  G03F1/54

    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed.

    Substrates, Structures Within A Scribe-Line Area Of A Substrate, And Methods Of Forming A Conductive Line Of A Redistribution Layer Of A Substrate And Of Forming A Structure Within A Scribe-Line Area Of The Substrate
    3.
    发明申请
    Substrates, Structures Within A Scribe-Line Area Of A Substrate, And Methods Of Forming A Conductive Line Of A Redistribution Layer Of A Substrate And Of Forming A Structure Within A Scribe-Line Area Of The Substrate 审中-公开

    公开(公告)号：US20190355631A1

    公开(公告)日：2019-11-21

    申请号：US15981619

    申请日：2018-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Shigeru Sugioka ,  Kiyonori Oyu ,  Hiroshi Toyama ,  Jung Chul Park ,  Raj K. Bansal

    IPC: H01L21/66 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad. The insulator material has a minimum elevational thickness from the conductive-test-pad uppermost surface to an uppermost surface of the insulator material that is immediately-adjacent the insulator-material opening and that is less than said minimum elevational thickness of the insulating material. Methods are disclosed.

    Semiconductor assemblies with system and methods for conveying signals using through mold vias
    4.
    发明授权
    Semiconductor assemblies with system and methods for conveying signals using through mold vias 有权

    公开(公告)号：US12230608B2

    公开(公告)日：2025-02-18

    申请号：US17478284

    申请日：2021-09-17

    Applicant: Micron Technology, Inc.

    Inventor： Travis M. Jensen ,  Raj K. Bansal

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.

    BOND PAD CONNECTION LAYOUT
    6.
    发明申请
    BOND PAD CONNECTION LAYOUT 有权

    公开(公告)号：US20220165701A1

    公开(公告)日：2022-05-26

    申请号：US17103834

    申请日：2020-11-24

    Applicant: Micron Technology, Inc.

    Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

    IPC: H01L23/00 ,  H01L25/18

    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

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