公开(公告)号：US20220359230A1

公开(公告)日：2022-11-10

申请号：US17315588

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Liang Chun Chen

IPC: H01L21/56 ,  H01L21/48

Abstract: Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.

公开(公告)号：US11955345B2

公开(公告)日：2024-04-09

申请号：US17315588

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Liang Chun Chen

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/56 ,  H01L21/4875 ,  H01L21/4878

Abstract: Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.

公开(公告)号：US20240266191A1

公开(公告)日：2024-08-08

申请号：US18620993

申请日：2024-03-28

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Liang Chun Chen

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/56 ,  H01L21/4875 ,  H01L21/4878

Abstract: Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.