公开(公告)号：US10911033B2

公开(公告)日：2021-02-02

申请号：US16392352

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K19/0185 ,  H03K3/356

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.

公开(公告)号：US20150356047A1

公开(公告)日：2015-12-10

申请号：US14297864

申请日：2014-06-06

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Don Morgan ,  Myung Gyoo Won

IPC: G06F13/42 ,  H03M13/05

CPC classification number: G06F13/4221 ,  H03M5/145 ,  H03M13/05 ,  H03M13/31

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract translation: 描述了用于执行数据总线反转操作（DBI）的装置和方法。 一个示例性设备包括一个DBI电路，被配置为并行地基于数据块来确定初始DBI位。 单独的初始DBI位与数据块的相应子块相关联。 DBI电路还被配置为基于初始DBI位串行确定DBI位。 DBI位中的各个与相应的子块相关联。 DBI电路还被配置为响应于具有特定逻辑值的相应的相关联的DBI位来反转各个子块的比特以提供DBI数据。 该装置还包括被配置为串行地输出DBI数据和DBI比特的子块的数据输出。

公开(公告)号：US11528015B2

公开(公告)日：2022-12-13

申请号：US17161546

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K19/0185 ,  H03K3/356

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

公开(公告)号：US20210152160A1

公开(公告)日：2021-05-20

申请号：US17161546

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K19/0185 ,  H03K3/356

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

公开(公告)号：US20200343880A1

公开(公告)日：2020-10-29

申请号：US16392352

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K3/356 ,  H03K19/0185

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.

公开(公告)号：US09405721B2

公开(公告)日：2016-08-02

申请号：US14297864

申请日：2014-06-06

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Don Morgan ,  Myung Gyoo Won

IPC: G06F13/42 ,  H03M13/05

CPC classification number: G06F13/4221 ,  H03M5/145 ,  H03M13/05 ,  H03M13/31

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract translation: 描述了用于执行数据总线反转操作（DBI）的装置和方法。 一个示例性设备包括一个DBI电路，被配置为并行地基于数据块来确定初始DBI位。 单独的初始DBI位与数据块的相应子块相关联。 DBI电路还被配置为基于初始DBI位串行确定DBI位。 DBI位中的各个与相应的子块相关联。 DBI电路还被配置为响应于具有特定逻辑值的相应的相关联的DBI位来反转各个子块的比特以提供DBI数据。 该装置还包括被配置为串行地输出DBI数据和DBI比特的子块的数据输出。