公开(公告)号：US20230236933A1

公开(公告)日：2023-07-27

申请号：US18156340

申请日：2023-01-18

Applicant: Micron Technology, Inc.

Inventor： Sandeep Krishna THIRUMALA ,  Lingming YANG ,  Amitava MAJUMDAR ,  Nevil GAJERA

IPC: G06F11/10 ,  G06F13/42

CPC classification number: G06F11/1076 ,  G06F11/1004 ,  G06F13/4221

Abstract: Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.