公开(公告)号：US11637175B2

公开(公告)日：2023-04-25

申请号：US17116120

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Hung-Wei Liu ,  Ning Lu ,  Anish A. Khandekar ,  Jeffery B. Hull ,  Silvia Borsari

IPC: H01L29/04 ,  H01L29/786

Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

公开(公告)号：US20220181434A1

公开(公告)日：2022-06-09

申请号：US17116120

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Hung-Wei Liu ,  Ning Lu ,  Anish A. Khandekar ,  Jeffery B. Hull ,  Silvia Borsari

IPC: H01L29/04 ,  H01L29/786

Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.