公开(公告)号：US12112828B2

公开(公告)日：2024-10-08

申请号：US17938002

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Carl L. Minifie ,  Phong T. Nguyen ,  Alexander A. Tomaso

IPC: G11C7/10 ,  G11C11/4076

CPC classification number: G11C7/109 ,  G11C7/1069 ,  G11C7/1093 ,  G11C11/4076

Abstract: Methods, systems, and devices for modification of a command timing pattern are described. A host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. Each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (CA) pin at the memory device. In some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). The host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. By dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.

公开(公告)号：US20250006235A1

公开(公告)日：2025-01-02

申请号：US18882478

申请日：2024-09-11

Applicant: Micron Technology, Inc.

Inventor： Carl L. Minifie ,  Phong T. Nguyen ,  Alexander A. Tomaso

IPC: G11C7/10 ,  G11C11/4076

Abstract: Methods, systems, and devices for modification of a command timing pattern are described. A host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. Each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (CA) pin at the memory device. In some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). The host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. By dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.

公开(公告)号：US20230162767A1

公开(公告)日：2023-05-25

申请号：US17938002

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Carl L. Minifie ,  Phong T. Nguyen ,  Alexander A. Tomaso

IPC: G11C7/10

CPC classification number: G11C7/109 ,  G11C7/1093 ,  G11C7/1069

Abstract: Methods, systems, and devices for modification of a command timing pattern are described. A host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. Each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (CA) pin at the memory device. In some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). The host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. By dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.