公开(公告)号：US20240282396A1

公开(公告)日：2024-08-22

申请号：US18581267

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： Sridhar Prudviraj Gunda ,  Thibash Rajamani Balakrishnan ,  Saurav Pundir ,  Sunil Singh Dhanik

IPC: G11C29/44

CPC classification number: G11C29/44

Abstract: Methods, systems, and devices for efficient performance of error rate detection procedures in a memory system are described. A memory system may determine whether a condition for performing an error rate detection procedure has been satisfied. Based on determining that the condition has been satisfied, the memory system may add a request for the error rate detection procedure to a queue. The memory system may then perform the error rate detection procedure indicated by the request in the queue based on determining that access activity from a host system has lapsed for a threshold duration.