公开(公告)号：US20240281162A1

公开(公告)日：2024-08-22

申请号：US18434375

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Thibash Rajamani Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0652 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for synchronizing operations between decks of a memory system are described. In some examples, a memory system may determine a PEC difference between sister decks of physical blocks of the memory system. A memory system controller may associate the sister decks with respective virtual blocks. The controller may scan each virtual block of the memory system to determine which blocks are to be recycled, and may generate a list of virtual blocks having a VPC that satisfies a first threshold. In some cases, the controller may perform one or more threshold comparisons to determine whether to perform the maintenance operation on the first sister deck or both the first sister deck and the second sister deck.

公开(公告)号：US20240282396A1

公开(公告)日：2024-08-22

申请号：US18581267

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： Sridhar Prudviraj Gunda ,  Thibash Rajamani Balakrishnan ,  Saurav Pundir ,  Sunil Singh Dhanik

IPC: G11C29/44

CPC classification number: G11C29/44

Abstract: Methods, systems, and devices for efficient performance of error rate detection procedures in a memory system are described. A memory system may determine whether a condition for performing an error rate detection procedure has been satisfied. Based on determining that the condition has been satisfied, the memory system may add a request for the error rate detection procedure to a queue. The memory system may then perform the error rate detection procedure indicated by the request in the queue based on determining that access activity from a host system has lapsed for a threshold duration.