公开(公告)号：US20250053525A1

公开(公告)日：2025-02-13

申请号：US18790156

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Gyan Prakash ,  Jose Rey C. De Luna ,  Srinivasa Aditya Regulagadda

IPC: G06F13/20

Abstract: A method includes receiving, via a decoder coupled to a feature register resident on a memory device interface that comprises a first feature register portion and a second feature portion, a bit string comprising at least one bit indicative of selection between the first feature register portion and the second feature register portion, and responsive to the at least one bit being indicative of selecting the first feature register portion, writing the bit string to at least one memory die among a plurality of memory dice addressed by the first feature register portion, or responsive to the at least one bit being indicative of selecting the second feature register portion, writing the bit string to at least one memory die among a plurality of memory dice addressed by the second feature register portion.