公开(公告)号：US20250165026A1

公开(公告)日：2025-05-22

申请号：US18949101

申请日：2024-11-15

Applicant: Micron Technology, Inc.

Inventor： Leonid Minz ,  Luigi Pilolli ,  Gyan Prakash

IPC: G06F1/06

Abstract: A method includes providing, by a controller, a plurality of control signals and a first plurality of clock signals to a memory device. In some embodiments, the first plurality of clock signals is greater than the plurality of control signals. The method can also include receiving, at the controller, a first plurality of data signals corresponding to the plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals from the memory device, and receiving, at the controller, a second plurality of data signals and a third plurality of clock signals corresponding to a second portion of the first plurality of clock signals from the memory device.

公开(公告)号：US20240363153A1

公开(公告)日：2024-10-31

申请号：US18639454

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Gyan Prakash ,  Nidhir Kumar ,  Sandeep Dwivedi

IPC: G11C29/12 ,  G11C29/20

CPC classification number: G11C7/22

Abstract: A method includes training a timing flip-flop circuit positioned between a controller and a memory resource, providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals, serializing the plurality of output clock signals and the plurality of output data signals, and providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.

公开(公告)号：US20250168131A1

公开(公告)日：2025-05-22

申请号：US18952670

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Leonid Minz ,  Luigi Pilolli ,  Gyan Prakash

IPC: H04L49/45 ,  H04L49/103 ,  H04L49/25

Abstract: A method includes receiving, by a memory device interface, a signal from a host that includes a header, decoding, by the memory device interface, the header to determine an instruction, selecting, by the memory device interface, a first channel associated with a first memory resource based on the instruction, sending, by the memory device interface, the header to a second channel associated with a second memory resource, and sending, by the memory device interface, subsequent packets of the header to the first channel.

公开(公告)号：US20250053341A1

公开(公告)日：2025-02-13

申请号：US18789249

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Gyan Prakash ,  Jose Rey C. De Luna

IPC: G06F3/06

Abstract: A method includes receiving, by a memory device interface, a first operation command targeted for receipt by a memory device coupled to the memory device interface causing, responsive to receiving the first operation command, a chip enable signal to be asserted in a first state to filter commands received by the memory device interface that are targeted for subsequent receipt by the memory device, receiving, by the memory device interface, a second operation command targeted for receipt by a memory device coupled to the memory device interface, and causing, responsive to receiving the second operation command, the chip enable signal to be asserted in a second state to allow commands received by the memory device interface that are targeted for subsequent receipt by the memory device to be received by the memory device.

公开(公告)号：US20250053525A1

公开(公告)日：2025-02-13

申请号：US18790156

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Gyan Prakash ,  Jose Rey C. De Luna ,  Srinivasa Aditya Regulagadda

IPC: G06F13/20

Abstract: A method includes receiving, via a decoder coupled to a feature register resident on a memory device interface that comprises a first feature register portion and a second feature portion, a bit string comprising at least one bit indicative of selection between the first feature register portion and the second feature register portion, and responsive to the at least one bit being indicative of selecting the first feature register portion, writing the bit string to at least one memory die among a plurality of memory dice addressed by the first feature register portion, or responsive to the at least one bit being indicative of selecting the second feature register portion, writing the bit string to at least one memory die among a plurality of memory dice addressed by the second feature register portion.