公开(公告)号：US20240064988A1

公开(公告)日：2024-02-22

申请号：US17900455

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Md Zahid Hossain ,  Martin Popp ,  Xiaosong Zhang ,  Surendranath C. Eruvuru ,  Suvra Sarkar ,  Tianqi Xu

IPC: H01L27/11573 ,  H01L27/11526

CPC classification number: H01L27/11573 ,  H01L27/11526

Abstract: A variety of applications can include apparatus having a memory device structured with a circuit under array (CuA) architecture. A page buffer region in the CuA can be formed with a periphery region that is horizontally adjacent to the page buffer region. Contacts to gates for transistors in the page buffer region can be formed to land only on these gates, separating and electrically isolating the contacts and associated gates from each other in the page buffer region. Contacts to gates for transistors in the periphery region can be formed to land on conductive regions disposed on gates for transistors in the periphery region.