公开(公告)号：US20250086282A1

公开(公告)日：2025-03-13

申请号：US18784133

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Lakshmi Kalpana K VAKATI ,  Dheeraj SRINIVASAN ,  Ting LUO ,  Zhenming ZHOU

IPC: G06F21/57

Abstract: In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.