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    ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
    1.
    发明申请
    ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES 有权

    公开(公告)号：US20250087277A1

    公开(公告)日：2025-03-13

    申请号：US18784022

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Zhenming ZHOU

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16

    Abstract: In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.

    SELECTION OF AN OPTIMAL SINGLE LEVEL CELL PROGRAMMING SCHEME
    3.
    发明申请
    SELECTION OF AN OPTIMAL SINGLE LEVEL CELL PROGRAMMING SCHEME 有权

    公开(公告)号：US20250022515A1

    公开(公告)日：2025-01-16

    申请号：US18767584

    申请日：2024-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Dheeraj SRINIVASAN ,  Michael G. MILLER ,  Zhenming ZHOU

    IPC: G11C16/10 ,  G11C16/34

    Abstract: In some implementations, a memory device may receive, from a host device, a program command. The memory device may determine that the program command is associated with a single level cell (SLC) program command. The memory device may determine a size of host data associated with the program command. The memory device may select a programming scheme, from multiple candidate programming schemes, to be used to write the host data to a memory based on the size of the host data and based on determining that the program command is associated with the SLC program command. The memory device may write the host data to the memory using the programming scheme.

    DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION
    4.
    发明申请
    DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION 有权

    公开(公告)号：US20240420783A1

    公开(公告)日：2024-12-19

    申请号：US18820480

    申请日：2024-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Zhenming ZHOU ,  Tomer Tzvi ELIASH

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

    Abstract: Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

    MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS
    6.
    发明公开
    MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS 审中-公开

    公开(公告)号：US20240046990A1

    公开(公告)日：2024-02-08

    申请号：US17817288

    申请日：2022-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Juane LI ,  Sead ZILDZIC, JR. ,  Zhenming ZHOU

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459

    Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

    MULTI-FINE PROGRAM SCHEME FOR RELIABILITY RISK WORD LINES
    7.
    发明申请
    MULTI-FINE PROGRAM SCHEME FOR RELIABILITY RISK WORD LINES 有权

    公开(公告)号：US20250103412A1

    公开(公告)日：2025-03-27

    申请号：US18786301

    申请日：2024-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Ching-Huang LU ,  Zhenming ZHOU ,  Jun WAN

    IPC: G06F11/00

    Abstract: In some implementations, a memory device may receive a program command instructing the memory device to program host data to a word line associated with a memory. The memory device may determine a program erase cycle (PEC) count associated with the word line. The memory device may determine, based on the PEC count, a selected program scheme to be used to program the host data to the word line, wherein the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme. The memory device may execute the program command by performing the selected program scheme.

    MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE
    8.
    发明公开
    MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE 审中-公开

    公开(公告)号：US20240256155A1

    公开(公告)日：2024-08-01

    申请号：US18629102

    申请日：2024-04-08

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Ching-Huang LU ,  Zhenming ZHOU

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

    RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME
    10.
    发明申请
    RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME 有权

    公开(公告)号：US20250086282A1

    公开(公告)日：2025-03-13

    申请号：US18784133

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Lakshmi Kalpana K VAKATI ,  Dheeraj SRINIVASAN ,  Ting LUO ,  Zhenming ZHOU

    IPC: G06F21/57

    Abstract: In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.

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