公开(公告)号：US12182024B2

公开(公告)日：2024-12-31

申请号：US18508141

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani ,  Venkatesh Anandpadmanabhan

IPC: G06F12/0862

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.

公开(公告)号：US11816035B2

公开(公告)日：2023-11-14

申请号：US17557406

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani ,  Venkatesh Anandpadmanabhan

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/6022

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; transmitting a response to the host system that indicates the data block is stored in a first buffer in host memory; determining the data block is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.