公开(公告)号：US20240071459A1

公开(公告)日：2024-02-29

申请号：US18237786

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Yaw Fann ,  Yu-Sheng Hsu

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/406 ,  G06F3/0623 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0683

Abstract: A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Rows of the memory device can also be updated based on a duration of time between receipt of the activation command for the row and a pre-charge command for the row. Row of the memory device clan further be updated utilizing a pair of counters that implement a ping pong mechanism to retain data between different consecutive durations of time.