公开(公告)号：US12175129B2

公开(公告)日：2024-12-24

申请号：US17968015

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Yu-Sheng Hsu ,  Chihching Chen

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

公开(公告)号：US20240086090A1

公开(公告)日：2024-03-14

申请号：US17944572

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yu-Sheng Hsu ,  Kang-Yong Kim ,  Ke Wei Chan

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/061 ,  G06F3/0673

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

公开(公告)号：US20240071459A1

公开(公告)日：2024-02-29

申请号：US18237786

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Yaw Fann ,  Yu-Sheng Hsu

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/406 ,  G06F3/0623 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0683

Abstract: A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Rows of the memory device can also be updated based on a duration of time between receipt of the activation command for the row and a pre-charge command for the row. Row of the memory device clan further be updated utilizing a pair of counters that implement a ping pong mechanism to retain data between different consecutive durations of time.

公开(公告)号：US20230342048A1

公开(公告)日：2023-10-26

申请号：US17660195

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20230342047A1

公开(公告)日：2023-10-26

申请号：US17660192

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US12260098B2

公开(公告)日：2025-03-25

申请号：US17944572

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yu-Sheng Hsu ,  Kang-Yong Kim ,  Ke Wei Chan

IPC: G06F3/06

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

公开(公告)号：US20250094091A1

公开(公告)日：2025-03-20

申请号：US18968260

申请日：2024-12-04

Applicant: Micron Technology, Inc.

Inventor： Yu-Sheng Hsu ,  Chihching Chen

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

公开(公告)号：US12204780B2

公开(公告)日：2025-01-21

申请号：US17660195

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20240126477A1

公开(公告)日：2024-04-18

申请号：US17968015

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Yu-Sheng Hsu ,  Chihching Chen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683

Abstract: Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.