Fuse array layout pattern and related apparatuses, systems, and methods

    公开(公告)号:US11942167B2

    公开(公告)日:2024-03-26

    申请号:US16799011

    申请日:2020-02-24

    IPC分类号: G11C17/18 G11C17/16 H10B20/20

    CPC分类号: G11C17/16 G11C17/18 H10B20/20

    摘要: Systems, methods, and apparatuses relating to interlocking transistor active regions are disclosed. An apparatus includes a gate including electrically conductive material and an active material including a doped semiconductor material. A portion of the active material overlapped by the gate has an at least substantially triangular shape. An apparatus includes a plurality of active materials. Each active material includes tapered ends and a plurality of gates. The plurality of active materials is arranged in an interlocking pattern with at least some tapered ends of the active materials interlocking with at least some others of the tapered ends. The plurality of gates overlaps the interlocked tapered ends of the plurality of active materials.

    FUSE ARRAY LAYOUT PATTERN AND RELATED APPARATUSES, SYSTEMS, AND METHODS

    公开(公告)号:US20210264997A1

    公开(公告)日:2021-08-26

    申请号:US16799011

    申请日:2020-02-24

    摘要: Systems, methods, and apparatuses relating to interlocking transistor active regions are disclosed. An apparatus includes a gate including electrically conductive material and an active material including a doped semiconductor material. A portion of the active material overlapped by the gate has an at least substantially triangular shape. An apparatus includes a plurality of active materials. Each active material of includes tapered ends and a plurality of gates. The plurality of active materials is arranged in an interlocking pattern with at least some tapered ends of the active materials interlocking with at least some others of the tapered ends. The plurality of gates overlaps the interlocked tapered ends of the plurality of active materials.