公开(公告)号：US5745731A

公开(公告)日：1998-04-28

申请号：US621061

申请日：1996-03-22

申请人： Min Hwahn Kim ,  Dong Woo Shin

发明人： Min Hwahn Kim ,  Dong Woo Shin

IPC分类号： G06F5/06 ,  G06F13/00

CPC分类号： G06F5/065

摘要： In accordance with the present invention, there is provided a dual channel FIFO circuit to perform bidirectional data transfer under the control of a host computer between a host interface and a small computer system interface, comprising: a first multiplexing means for selecting one of the data from said host interface and the data from said small computer system interface; a single ported SRAM for storing the selected data by said first multiplexing means and outputting the data, which are indicated by pointers, according to the requests from said host interface or said small computer system interface; a second multiplexing means for selecting one of the data from said single ported SRAM and the data from said small computer system interface; a first staging memory means for storing the data to be outputted to said host interface; and a second staging memory means for storing the selected data by said second multiplexing means and transferring them to said second multiplexing means and said small computer system interface.

摘要翻译： 根据本发明，提供了一种双通道FIFO电路，用于在主机接口和小型计算机系统接口之间的主计算机的控制下执行双向数据传输，包括：第一多路复用装置，用于选择一个数据 从所述主机接口和来自所述小型计算机系统接口的数据; 单端口SRAM，用于存储所述第一复用装置所选择的数据，并根据来自所述主机接口或所述小型计算机系统接口的请求，输出由指针指示的数据; 第二复用装置，用于从所述单端口SRAM中选择一个数据和来自所述小型计算机系统接口的数据; 第一分段存储装置，用于存储要输出到所述主机接口的数据; 以及第二分段存储装置，用于通过所述第二多路复用装置存储所选择的数据并将其传送到所述第二多路复用装置和所述小型计算机系统接口。

公开(公告)号：US07698680B2

公开(公告)日：2010-04-13

申请号：US11646435

申请日：2006-12-28

申请人： Min Hwahn Kim

发明人： Min Hwahn Kim

IPC分类号： G06F17/50 ,  H01L29/80 ,  H01L21/8238

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at least one PMOS transistor with a first power voltage; and a second power layer supplying the at least one NMOS transistor with a second power voltage. The first poly gate of the PMOS transistor is isolated from the second poly gate of the NMOS transistor.

摘要翻译： 提供了工程变更单（ECO）单元，其包括：功能电路，其包括具有P扩散层和第一多晶硅栅极的至少一个PMOS晶体管，至少一个具有N扩散层的NMOS晶体管和第二 多门 向所述至少一个PMOS晶体管提供第一电源电压的第一电源层; 以及向所述至少一个NMOS晶体管提供第二电源电压的第二功率层。 PMOS晶体管的第一多晶硅栅极与NMOS晶体管的第二多晶硅栅极隔离。

公开(公告)号：US20070157151A1

公开(公告)日：2007-07-05

申请号：US11646435

申请日：2006-12-28

申请人： Min Hwahn Kim

发明人： Min Hwahn Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at least one PMOS transistor with a first power voltage; and a second power layer supplying the at least one NMOS transistor with a second power voltage. The first poly gate of the PMOS transistor is isolated from the second poly gate of the NMOS transistor.

摘要翻译： 提供了工程变更单（ECO）单元，其包括：功能电路，其包括具有P扩散层和第一多晶硅栅极的至少一个PMOS晶体管，至少一个具有N扩散层的NMOS晶体管和第二 多门 向所述至少一个PMOS晶体管提供第一电源电压的第一电源层; 以及向所述至少一个NMOS晶体管提供第二电源电压的第二功率层。 PMOS晶体管的第一多晶硅栅极与NMOS晶体管的第二多晶硅栅极隔离。

公开(公告)号：US6057720A

公开(公告)日：2000-05-02

申请号：US74175

申请日：1998-05-07

申请人： Min Hwahn Kim

发明人： Min Hwahn Kim

IPC分类号： G06F7/525 ,  G06F5/01 ,  G06F7/00 ,  G06M3/00

CPC分类号： G06F5/015 ,  G06F7/49952

摘要： The present invention has been made in view of the above mentioned problem, and the present invention provides a sticky signal generator for rapidly generating a sticky signal with a small layout area which uses a shift register of which the size is equal to the size of the inputted operand data. In accordance with the present invention, there is disclosed a sticky signal generator including: a plurality of shifters for shifting an input data by a shifting width in response to at least one of shifting width control signal, wherein the size of the shifters is equal to the size of the input data, and the plurality of shifters are coupled serially to each other; a plurality of selectors for selecting and outputting the bits which are discarded by the shifters during shifting operation in response to the at least one of shifting width control signal, wherein each input terminal of the plurality of selectors are coupled to each of corresponding shifters; and a detector for determining if a bit of predetermined logic level is included in at least one of outputs from the plurality of selectors, and outputting a sticky signal in case the bit of predetermined logic level is included in at least one of the outputs.

摘要翻译： 本发明是鉴于上述问题而做出的，本发明提供了一种粘性信号发生器，其用于快速产生具有小布局面积的粘性信号，其使用尺寸等于 输入操作数数据。 根据本发明，公开了一种粘性信号发生器，包括：多个移位器，用于响应于移位宽度控制信号中的至少一个移位输入数据移位宽度，其中移位器的大小等于 输入数据的大小和多个移位器彼此串联耦合; 多个选择器，用于响应于所述移位宽度控制信号中的至少一个，选择和输出由移位器在移位操作期间丢弃的比特，其中所述多个选择器中的每个输入端耦合到每个对应的移位器; 以及检测器，用于确定来自多个选择器的输出中的至少一个中是否包括预定逻辑电平的位，并且在至少一个输出中包括预定逻辑电平的位的情况下输出粘性信号。

公开(公告)号：US07683667B2

公开(公告)日：2010-03-23

申请号：US11869408

申请日：2007-10-09

申请人： Min Hwahn Kim

发明人： Min Hwahn Kim

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： Embodiments relate to a level shifter which uses a single voltage source, has an excellent operation characteristic even when a difference between a low voltage and a high voltage is large, and can be easily designed. Embodiments relate to a level shifter for shifting a voltage level between an input terminal connected to a circuit block which operates by a low voltage source and an output terminal connected to a circuit block which operates by a high voltage source. In embodiments, the level shifter may include a pull-up PMOS and a pull-down NMOS, both of which are connected between the high voltage source and ground in the form of an inverter and have an output node connected to the output terminal. The level shifter may include a control node which is connected to inputs of the pull-up and pull-down NMOS in the form of the inverter. The level shifter may have an input gate for connecting the control node to the high voltage source or ground according to a voltage level of the input terminal. The level shifter may also include a first feedback chain which is connected between the control node and the input gate and disconnects the input gate and the high voltage source when the voltage level of the input terminal is high and the input gate connects the control node to ground.

摘要翻译： 实施例涉及使用单个电压源的电平移位器，即使当低电压和高电压之间的差异大时也具有优异的操作特性，并且可以容易地设计。 实施例涉及一种电平移位器，用于使连接到由低电压源操作的电路块的输入端与连接到由高电压源操作的电路块的输出端之间的电压电平进行移位。 在实施例中，电平移位器可以包括上拉PMOS和下拉NMOS，它们都以逆变器的形式连接在高电压源和地之间，并具有连接到输出端的输出节点。 电平移位器可以包括以逆变器的形式连接到上拉和下拉NMOS的输入的控制节点。 电平移位器可以具有用于根据输入端子的电压电平将控制节点连接到高电压源或地的输入门。 电平移位器还可以包括第一反馈链，其连接在控制节点和输入门之间，并且当输入端的电压电平高并且输入门将控制节点连接到 地面。

公开(公告)号：US5917339A

公开(公告)日：1999-06-29

申请号：US777207

申请日：1996-12-27

申请人： Min Hwahn Kim

发明人： Min Hwahn Kim

IPC分类号： G11C7/00 ,  H03K19/0185

CPC分类号： H03K19/018521

摘要： In a mixed voltage input buffer for managing mixed voltages in a semiconductor device which uses various voltages, includes a transmission unit for inputting a given signal and transmitting the input signal according to an enable signal, and a voltage level conversion unit for inputting an output signal of the transmission unit and converting its voltage level into a voltage level of an inner core power and then outputting it.

摘要翻译： 在用于管理使用各种电压的半导体装置中的混合电压的混合电压输入缓冲器中，包括用于输入给定信号并根据使能信号发送输入信号的传输单元和用于输入输出信号的电压电平转换单元 并将其电压电平转换成内核功率的电压电平，然后将其输出。