公开(公告)号：US20050032386A1

公开(公告)日：2005-02-10

申请号：US10634001

申请日：2003-08-04

申请人： Ming-Ching Chang ,  Li-Te Lin ,  Yu-I Wang ,  Yuan-Hung Chiu ,  Hui-Jan Tao

发明人： Ming-Ching Chang ,  Li-Te Lin ,  Yu-I Wang ,  Yuan-Hung Chiu ,  Hui-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/3213 ,  H01L21/461 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/32137

摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.

摘要翻译： 一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅 蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。