公开(公告)号：US08397197B1

公开(公告)日：2013-03-12

申请号：US13115858

申请日：2011-05-25

Applicant: Mitrajit Chatterjee ,  Sandeep Badida

Inventor： Mitrajit Chatterjee ,  Sandeep Badida

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/84

Abstract: A circuit analysis tool is provided, enabled as computer software instructions, for budgeting time delays between integrated circuit (IC) modules. The instructions accept a command enabling an IC floor-plan including a first module and a second module. The first module includes a first circuit element having a signal output interface, and an output port. The second module includes an input port, and a second circuit element having a signal input interface. A command is accepted defining a maximum delay value, and a first delay value is estimated between the first circuit element signal output interface and the first module output port. A second delay value is estimated between the second circuit element signal input interface and the second module input port, and a third delay value is estimated between the first module output port and the second module input port. The first, second, and third delay values are summed, creating a time budget estimate. The time budget estimate is approved if it is less than the maximum delay value.

Abstract translation: 提供电路分析工具，作为计算机软件指令，用于对集成电路（IC）模块之间的时间延迟进行预算。 指令接受启用包括第一模块和第二模块的IC平面图的命令。 第一模块包括具有信号输出接口的第一电路元件和输出端口。 第二模块包括输入端口和具有信号输入接口的第二电路元件。 接受定义最大延迟值的命令，并且在第一电路元件信号输出接口和第一模块输出端口之间估计第一延迟值。 在第二电路元件信号输入接口和第二模块输入端口之间估计第二延迟值，并且在第一模块输出端口和第二模块输入端口之间估计第三延迟值。 将第一，第二和第三延迟值相加，创建时间预算估计。 如果小于最大延迟值，则批准时间预算估算值。