VIDEO DECODING APPARATUS AND METHOD BASED ON A DATA AND FUNCTION SPLITTING SCHEME
    2.
    发明申请
    VIDEO DECODING APPARATUS AND METHOD BASED ON A DATA AND FUNCTION SPLITTING SCHEME 有权
    基于数据和功能分割方案的视频解码设备和方法

    公开(公告)号:US20110116550A1

    公开(公告)日:2011-05-19

    申请号:US12837022

    申请日:2010-07-15

    IPC分类号: H04N11/02

    摘要: A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.

    摘要翻译: 公开了一种基于数据和功能分解方案的视频解码装置和方法。 基于数据和功能分割方案的视频解码装置包括:可变长度解码单元,对比特流执行可变长度解码和解析以获取残差数据和解码参数,并且逐行分割残留数据和解码参数; 并且N(N是2或更大的自然数)将数量分解解量化和逆离散余弦变换(IDCT),运动矢量预测,帧内预测和运动补偿,视频恢复和去块功能的簇数分为M个函数,获取 按照列逐列的残差数据,解码参数和宏块(MB)处理信息,并将通过列获取的信息拆分为M个函数以进行处理。

    Video decoding apparatus and method based on a data and function splitting scheme
    4.
    发明授权
    Video decoding apparatus and method based on a data and function splitting scheme 有权
    基于数据和功能分割方案的视频解码装置和方法

    公开(公告)号:US08559524B2

    公开(公告)日:2013-10-15

    申请号:US12837022

    申请日:2010-07-15

    IPC分类号: H04N7/26

    摘要: A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.

    摘要翻译: 公开了一种基于数据和功能分解方案的视频解码装置和方法。 基于数据和功能分割方案的视频解码装置包括:可变长度解码单元,对比特流执行可变长度解码和解析以获取残差数据和解码参数,并且逐行分割残留数据和解码参数; 并且N(N是2或更大的自然数)将数量分解解量化和逆离散余弦变换(IDCT),运动矢量预测,帧内预测和运动补偿,视频恢复和去块功能的簇数分为M个函数,获取 按照列逐列的残差数据,解码参数和宏块(MB)处理信息,并将通过列获取的信息拆分为M个函数以进行处理。

    H.264 CAVLC DECODING METHOD BASED ON APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR
    6.
    发明申请
    H.264 CAVLC DECODING METHOD BASED ON APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR 失效
    基于应用特定指令集处理器的H.264 CAVLC解码方法

    公开(公告)号:US20090138684A1

    公开(公告)日:2009-05-28

    申请号:US12181769

    申请日:2008-07-29

    IPC分类号: G06F9/30

    CPC分类号: H04N19/42 H04N19/44 H04N19/91

    摘要: Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.

    摘要翻译: 提供了一种基于应用特定指令集处理器(ASIP)的H.264上下文自适应可变长度编码(CAVLC)解码方法。 H.264 CAVLC解码方法包括:基于解码系数的表确定多个比较比特串,将比较比特列的长度存储在第一寄存器中,将比较比特列的代码值存储在第二寄存器 根据比较比特串的长度和码值比较输入比特流与比较比特串,并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。 该方法使用ASIP中的寄存器提取解码系数,而不访问存储器,并且防止由存储器访问引起的速度降低,从而提高H.264解码器的解码速度。

    VIDEO DECODING APPARATUS AND METHOD BASED ON MULTIPROCESSOR
    7.
    发明申请
    VIDEO DECODING APPARATUS AND METHOD BASED ON MULTIPROCESSOR 审中-公开
    基于多处理器的视频解码设备和方法

    公开(公告)号:US20110085601A1

    公开(公告)日:2011-04-14

    申请号:US12836979

    申请日:2010-07-15

    IPC分类号: H04N7/26

    CPC分类号: H04N19/436 H04N19/44

    摘要: Disclosed are a multiprocessor-based video decoding apparatus and method. The multiprocessor-based video decoding apparatus includes: a stream parser dividing an input stream by row and parsing a skip counter and a quantization parameter of the input stream; and a plurality of processors acquiring the plurality of divided streams, the skip counter, and the quantization parameter generated by the stream parser, acquiring decoded information of an upper processor among neighboring processors by row, and parallel-decoding the plurality of divided streams by row. Decoding of an input stream can be parallel-processed by row.

    摘要翻译: 公开了一种基于多处理器的视频解码装置和方法。 基于多处理器的视频解码装置包括:流分析器,其逐行分割输入流,解析跳过计数器和输入流的量化参数; 以及多个处理器,获取多个划分的流,跳过计数器和由流解析器生成的量化参数,通过行获取相邻处理器之间的上位处理器的解码信息,并且按行并行解码多个划分的流 。 输入流的解码可以由行并行处理。

    H.264 CAVLC decoding method based on application-specific instruction-set processor
    8.
    发明授权
    H.264 CAVLC decoding method based on application-specific instruction-set processor 失效
    基于应用特定指令集处理器的H.264 CAVLC解码方法

    公开(公告)号:US07646318B2

    公开(公告)日:2010-01-12

    申请号:US12181769

    申请日:2008-07-29

    IPC分类号: H03M7/00

    CPC分类号: H04N19/42 H04N19/44 H04N19/91

    摘要: Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.

    摘要翻译: 提供了一种基于应用特定指令集处理器(ASIP)的H.264上下文自适应可变长度编码(CAVLC)解码方法。 H.264 CAVLC解码方法包括:基于解码系数的表确定多个比较比特串,将比较比特列的长度存储在第一寄存器中,将比较比特列的代码值存储在第二寄存器 根据比较比特串的长度和码值比较输入比特流与比较比特串,并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。 该方法使用ASIP中的寄存器提取解码系数,而不访问存储器,并且防止由存储器访问引起的速度降低,从而提高H.264解码器的解码速度。

    Apparatus for decoding residual data based on bit plane and method thereof
    9.
    发明授权
    Apparatus for decoding residual data based on bit plane and method thereof 失效
    用于基于位平面解码残差数据的装置及其方法

    公开(公告)号:US08638859B2

    公开(公告)日:2014-01-28

    申请号:US13226765

    申请日:2011-09-07

    IPC分类号: H04N7/12 H04N11/02

    摘要: An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.

    摘要翻译: 一种用于解码基于位平面的残差数据的装置及其方法,其能够实现并行解码系统中的存储器与功能模块之间的数据流量的显着降低,包括:可变长度解码模块,被配置为产生残留数据, 来自位流的每个宏块将残差数据分成组,并且生成关于每个组的位平面;以及可变长度解码存储器,被配置为存储从可变长度解码模块生成的位平面,并存储 该组根据位平面的值。

    APPARATUS FOR DECODING RESIDUAL DATA BASED ON BIT PLANE AND METHOD THEREOF
    10.
    发明申请
    APPARATUS FOR DECODING RESIDUAL DATA BASED ON BIT PLANE AND METHOD THEREOF 失效
    用于根据位平面解码残留数据的装置及其方法

    公开(公告)号:US20120128075A1

    公开(公告)日:2012-05-24

    申请号:US13226765

    申请日:2011-09-07

    IPC分类号: H04N7/26

    摘要: An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.

    摘要翻译: 一种用于解码基于位平面的残差数据的装置及其方法,其能够实现并行解码系统中的存储器与功能模块之间的数据流量的显着降低,包括:可变长度解码模块,被配置为产生残留数据, 来自位流的每个宏块将残差数据分成组,并且生成关于每个组的位平面;以及可变长度解码存储器,被配置为存储从可变长度解码模块生成的位平面,并存储 该组根据位平面的值。