摘要:
Provided are a multi-processor system and a multi-processing method in the multi-processor system. The multi-processor system comprises a plurality of processors each including a data core and a processing core; and switches connecting the data core to the processing core in each of the processors as a combination of a data core-processing core pair. Therefore, the multi-processor system may be useful to remove any overhead for communications and make programming easy and simple.
摘要:
A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.
摘要:
Provided is a table generation method of decoding a variable-length code. The table generation method includes receiving a variable-length code table and a search width N, generating a K-ary tree from the variable-length code table and the search width N, and generating an N-bit code table from the K-ary tree.
摘要:
A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.
摘要:
Provided is a table generation method of decoding a variable-length code. The table generation method includes receiving a variable-length code table and a search width N, generating a K-ary tree from the variable-length code table and the search width N, and generating an N-bit code table from the K-ary tree.
摘要:
Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.
摘要:
Disclosed are a multiprocessor-based video decoding apparatus and method. The multiprocessor-based video decoding apparatus includes: a stream parser dividing an input stream by row and parsing a skip counter and a quantization parameter of the input stream; and a plurality of processors acquiring the plurality of divided streams, the skip counter, and the quantization parameter generated by the stream parser, acquiring decoded information of an upper processor among neighboring processors by row, and parallel-decoding the plurality of divided streams by row. Decoding of an input stream can be parallel-processed by row.
摘要:
Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.
摘要:
An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.
摘要:
An apparatus for decoding residual data based on a bit plane and a method thereof, capable of achieving a significant reduction in data traffic between a memory and a functional module in a parallel decoding system, include a variable length decoding module configured to generate residual data for each macroblock from a bit stream, divide the residual data into groups, and generate a bit plane regarding each of the groups, and a variable length decoding memory configured to store the bit plane generated from the variable length decoding module and store the residual data of the groups according to a value of the bit plane.