公开(公告)号：US20040164769A1

公开(公告)日：2004-08-26

申请号：US10730002

申请日：2003-12-09

申请人： Mosaid Technologies, Inc

发明人： Raymond Jit-Hung Sung ,  Duncan George Elliott

IPC分类号： H03K019/096

CPC分类号： H03K19/0963

摘要： A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

摘要翻译： 提供了一种用于单轨多米诺骨牌逻辑电路的系统方法，其中反相和非单调逻辑功能可以集成到几乎零开销的流水线系统中。 这种称为时钟逻辑（CL）-domino的逻辑系列功能完整，同时容忍偏差并最小化必须分配的时钟相位数。 在高偏移（1-FO4）条件下，1GHz下的CL-domino ALU的仿真结果显示，在双轨偏斜容忍多米诺骨牌逻辑中实现的相同ALU的功率降低了41％。 尽管在某些情况下还需要额外的设计工作，但是这种功率降低不会对双轨技术造成性能损失。

公开(公告)号：US20030179012A1

公开(公告)日：2003-09-25

申请号：US10395318

申请日：2003-03-21

申请人： MOSAID Technologies, Inc.

发明人： Raymond Jit-Hung Sung ,  John Conrad Koob ,  Tyler Lee Brandon ,  Duncan George Elliot

IPC分类号： H03K019/094

CPC分类号： H04L5/1461

摘要： A circuit and method for accelerating bus line communication in an integrated circuit is disclosed. High speed transmission of signals along a bus line is achieved by driving a series of bus line segments with their own bi-directional bus amplification circuits. Because each bus line segment has less capacitive loading than longer non-segmented bus lines, voltage reversal, or data inversion of a pair of complementary lines of a bus line segment is accomplished at high speed. Each bi-directional bus amplification circuit includes a precharge circuit for precharging each complementary pair of lines to known logic levels, and a drive circuit for changing the logic level of each line. The bi-directional bus amplification circuit of the present invention logically connects two lines to each other while actively amplifying the signal in either direction without prior knowledge of which direction the signal must be driven, and without additional control overhead than that required for a conventional precharged bus line.

摘要翻译： 公开了一种用于加速集成电路中的总线通信的电路和方法。 通过用自己的双向总线放大电路驱动一系列总线线段，实现沿总线线路的信号的高速传输。 因为每个总线段具有比较长的非分段总线线路更少的电容负载，所以高速地实现总线线段的一对互补线的电压反转或数据反转。 每个双向总线放大电路包括预充电电路，用于将每条互补线对预充电到已知逻辑电平，以及用于改变每条线的逻辑电平的驱动电路。 本发明的双向总线放大电路逻辑上将两条线彼此逻辑地连接，同时在任一方向上主动放大信号，而不需要先前知道信号必须被驱动的方向，而不需要额外的控制开销，而不需要常规的预充电 公车线。

公开(公告)号：US20030179631A1

公开(公告)日：2003-09-25

申请号：US10395656

申请日：2003-03-21

申请人： MOSAID Technologies, Inc.

发明人： John Conrad Koob ,  Raymond Jit-Hung Sung ,  Tyler Lee Brandon ,  Duncan George Elliott

IPC分类号： H03K019/177

CPC分类号： H03K17/693

摘要： A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.

摘要翻译： 公开了用于阵列并行处理器设备的列冗余架构。 特别地，通过将​​处理元件内的旁路电路设置为禁用，特别地，在缺陷存储器列及其相关联的处理元件被禁用之后，处理元件之间的菊花链式通信被保留。 地址重映射电路确保可以以线性列顺序来寻址替代有缺陷的存储器列和处理元件的备用存储器列和相关联的处理元件。 列冗余架构是灵活的，因为它允许替换任意数量的相邻处理元件以及不相邻的处理元件，对设备性能的影响最小。