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    Spare cell architecture for fixing design errors in manufactured integrated circuits
    4.
    发明申请
    Spare cell architecture for fixing design errors in manufactured integrated circuits 失效
    用于在制造的集成电路中修复设计错误的备用电池架构

    公开(公告)号：US20040080334A1

    公开(公告)日：2004-04-29

    申请号：US10352470

    申请日：2003-01-27

    发明人： Alain Vergnes

    IPC分类号： H03K019/177

    CPC分类号： H03K19/17764 ,  H03K19/1774 ,  H03K19/17796

    摘要： A fully self-sufficient configurable spare gate cell that has two types of inputs: a functional input bus and an equation input bus, whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. In a spare state, the functional input buses are connected to an area of pre-defined logic where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

    摘要翻译： 具有两种类型的输入的完全自给的可配置备用门控单元：功能输入总线和方程式输入总线，由此通过将某些信号的断言转换为等式输入，备用门单元可以变换成任何乘积运算的总和 总线。 在备用状态下，功能输入总线连接到预定义逻辑区域，其中对错误修复的需求很高。 因此，在芯片设计的布局和布线阶段期间，备用单元将自动放置在错误修复区域附近，从而减少了查找路由通道的需要。

    Programmable logic array integrated circuits
    5.
    发明申请
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US20040066212A1

    公开(公告)日：2004-04-08

    申请号：US10356691

    申请日：2003-01-31

    申请人： Altera Corporation

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

    IPC分类号： H03K019/177

    CPC分类号： H03K19/17736 ,  G01R31/318516 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (nullLABsnull). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

    Heterogeneous interconnection architecture for programmable logic devices
    6.
    发明申请
    Heterogeneous interconnection architecture for programmable logic devices 失效
    用于可编程逻辑器件的异构互连架构

    公开(公告)号：US20040017222A1

    公开(公告)日：2004-01-29

    申请号：US10449753

    申请日：2003-05-30

    申请人： Altera Toronto Co.

    发明人： Vaughn Betz ,  Jonathan Rose

    IPC分类号： H03K019/177

    CPC分类号： H03K19/17736 ,  H03K19/17704

    摘要： An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

    摘要翻译： 提出了一种用于可编程逻辑器件（PLD）的互连结构，其中异构互连资源可以根据两个或多个操作参数（例如信号传播速度，电路面积，信号路由灵活性）可编程地连接到功能块， 和PLD可靠性。 可编程互连资源包括不平衡多路复用器，不同类型的接口缓冲器和不同宽度和不同线对线间距的信号线。

    Customizable and programmable cell array
    8.
    发明申请
    Customizable and programmable cell array 有权
    可定制和可编程单元阵列

    公开(公告)号：US20030206036A1

    公开(公告)日：2003-11-06

    申请号：US10452049

    申请日：2003-06-03

    申请人： eASIC Corporation

    发明人： Zvi Or-Bach

    IPC分类号： H03K019/177

    CPC分类号： H01L27/118 ,  G06F17/5054 ,  H03K19/1732 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17796

    摘要： A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

    摘要翻译： 一种可个性化和可编程的集成电路装置，其包括至少第一和第二可编程逻辑单元以及互连所述至少第一和第二可编程逻辑单元以用于集成电路装置的个性化的至少一个永久导电通路，其中所述至少第一和第二可编程逻辑单元 逻辑单元可通过向其施加电信号来编程。

    Line segmentation in programmable logic devices having redundancy circuitry
    9.
    发明申请
    Line segmentation in programmable logic devices having redundancy circuitry 有权

    公开(公告)号：US20030201793A1

    公开(公告)日：2003-10-30

    申请号：US10422007

    申请日：2003-04-22

    申请人： Altera Corporation

    发明人： Triet Nguyen ,  Changsong Zhang ,  David Jefferson

    IPC分类号： H03K019/177

    CPC分类号： H03K19/17764 ,  G11C29/70 ,  H03K19/17728 ,  H03K19/17736

    摘要： Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.