公开(公告)号：US5519627A

公开(公告)日：1996-05-21

申请号：US339928

申请日：1994-11-15

申请人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Christopher H. Kingsley

发明人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Christopher H. Kingsley

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and control logic. The control logic is implemented in standard cells or gate arrays using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath elements, including both structural components and computational components, where some of the computational components are complex circuits having multiple, parallel outputs. Each computational component has associated therewith a set of one or more datapath expressions performed thereby. The received HDL circuit specification is converted into circuit data structures representing the circuit's datapath expressions and structural components. The datapath synthesizer locates all datapath elements in said library matching each such datapath expression and structural component. Then an optimizer determines which datapath expressions can be "combined", or performed by a single library element, so as to reduce the circuit layout area used. The optimizer can combine multiple datapath expressions so as to use datapath circuit elements having multiple parallel outputs. Finally, one library element is selected for each datapath expression, or combined expression, on the basis of circuit area, speed, power or other optimization criteria. Then the connections between the selected circuit components are computed and the resulting circuit is output in the form of a circuit netlist.

摘要翻译： 数据路径电路合成器将HDL电路规范转换为电路网表。 指定电路的行为描述分为两个不同的部分：数据路径逻辑和控制逻辑。 控制逻辑使用逻辑合成器在标准单元或门阵列中实现。 数据路径逻辑使用具有数据路径元素库（包括结构组件和计算组件）的数据路径合成器进行最佳合成，其中一些计算组件是具有多个并行输出的复杂电路。 每个计算组件都具有与之相关的一组一个或多个数据路径表达式。 接收的HDL电路规范被转换成表示电路的数据路径表达式和结构组件的电路数据结构。 数据路径合成器定位所有库中的所有数据路径元素，以匹配每个这样的数据路径表达式和结构组件。 然后，优化器确定哪个数据路径表达式可以“组合”，或由单个库元素执行，以便减少使用的电路布局面积。 优化器可以组合多个数据路径表达式，以便使用具有多个并行输出的数据通路电路元件。 最后，基于电路面积，速度，功率或其他优化标准，为每个数据路径表达式或组合表达式选择一个库元素。 然后计算所选择的电路部件之间的连接，并且所得到的电路以电路网表的形式输出。

公开(公告)号：US5726902A

公开(公告)日：1998-03-10

申请号：US482267

申请日：1995-06-07

申请人： Mossaddeq Mahmood ,  Mandalagiri Chandrasekhar ,  Arnold Ginetti ,  Balmukund K. Sharma

发明人： Mossaddeq Mahmood ,  Mandalagiri Chandrasekhar ,  Arnold Ginetti ,  Balmukund K. Sharma

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath cells and a gate library including primitive gate cells are provided, and a netlist is synthesized from the HDL description. The netlist is composed of datapath cells from the datapath library and primitive gate cells from the gate library. If a datapath cell instance in the netlist does not meet the timing constraints imposed by a user for the circuit, an alternative datapath cell instance can be substituted for that cell instance in a resynthesis and optimization step. An integrated circuit is preferably fabricated as specified by the resynthesized netlist. The netlist is preferably resynthesized multiple times in an iterative loop to optimize the netlist according to the constraints. The timing information for alternative cells used in the resynthesis of the netlist can be retrieved from a timing database in one embodiment. Timing information for datapath cells is stored in the timing database in a pre-characterization process, and the location of the timing information in the timing database is stored in a query database. In another embodiment, timing information for alternative datapath cells is calculated dynamically during the resynthesis process for optimizing the timing of a netlist.

摘要翻译： 一种用于表征集成电路设计和制造中数据通路的时序特性的方法和装置。 用于集成电路的一组电路规范以硬件描述语言（HDL）描述开发和描述。 提供包括数据路径单元和包括原始门单元的门库的数据路径库，并且从HDL描述合成网表。 网表由数据路径库的数据路径单元和门库的原始门单元组成。 如果网表中的数据路径小区实例不满足用户对该电路施加的时序约束，则可以在再合成和优化步骤中替代该数据路径小区实例来替换该小区实例。 优选地，由再合成网表规定制造集成电路。 网表优选在迭代循环中重新合成多次，以根据约束优化网表。 在一个实施例中，可以从定时数据库检索用于网表重新合成中的备选单元的定时信息。 用于数据通路单元的定时信息在预定制过程中存储在定时数据库中，定时数据库中定时信息​​的位置存储在查询数据库中。 在另一个实施例中，在用于优化网表的定时的再合成过程期间动态地计算替代数据路径小区的定时信息。

公开(公告)号：US5491640A

公开(公告)日：1996-02-13

申请号：US272205

申请日：1994-07-08

申请人： Balmukund K. Sharma ,  Mossaddeq Mahmood

发明人： Balmukund K. Sharma ,  Mossaddeq Mahmood

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5045

摘要： A method for fabricating an integrated circuit includes the steps of: (a) developing a set of circuit specifications for an integrated circuit; (b) encoding the set of circuit specifications in a hardware description language (HDL); (c) synthesizing a netlist including a sequential datapath with a datapath synthesizer from the HDL; and (d) fabricating an integrated circuit as specified by the netlist. A method for datapath synthesis includes the steps of: (a) providing a datapath library including sequential components and combinational components; (b) developing a set of circuit specifications for an integrated circuit; (c) encoding the set of circuit specifications in a HDL; (d) developing a number of IC expression trees derived from the HDL; (e) matching the IC expression trees with library expression trees derived from the datapath library to provide a map of matches; and (f) synthesizing according to the map to create a datapath netlist including both sequential datapaths and combinational datapaths. A datapath synthesizer includes a digital processor, memory coupled to the digital processor, and a datapath library stored in the memory. An input device is used to input a HDL description of circuit specifications into memory, and an IC expression generator develops a number of IC expression trees from the HDL. A matcher compares the plurality of IC expression trees with library expression trees derived from the datapath library to provide a map of matches, and a synthesizer provides a netlist including both sequential datapaths and combinational datapaths according to the map.

摘要翻译： 一种用于制造集成电路的方法包括以下步骤：（a）开发用于集成电路的一组电路规范; （b）以硬件描述语言（HDL）对该组电路规范进行编码; （c）从HDL合成包括数据通路合成器的顺序数据路径的网表; 和（d）制造由网表规定的集成电路。 一种用于数据通路合成的方法包括以下步骤：（a）提供包括顺序分量和组合分量的数据路径库; （b）为集成电路开发一套电路规范; （c）以HDL编码该组电路规格; （d）开发一些源自HDL的IC表达树; （e）将IC表达式树与从数据路径库派生的库表达式树匹配以提供匹配的映射; 和（f）根据地图合成以创建包括顺序数据路径和组合数据路径两者的数据路径网表。 数据路径合成器包括数字处理器，耦合到数字处理器的存储器和存储在存储器中的数据路径库。 输入装置用于将电路规格的HDL描述输入到存储器中，并且IC表达式生成器从HDL开发许多IC表达树。 匹配器将多个IC表达式树与从数据路径库导出的库表达式树进行比较，以提供匹配映射，并且合成器根据地图提供包括顺序数据路径和组合数据路径的网表。

公开(公告)号：US5764525A

公开(公告)日：1998-06-09

申请号：US442290

申请日：1995-05-16

申请人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Arnold Ginetti ,  Francois Silve

发明人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Arnold Ginetti ,  Francois Silve

IPC分类号： G06F17/50 ,  G06F15/00

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

摘要翻译： 描述一种设计电路的方法。 生成电路的网表。 然后执行网表的分析以产生一组细胞实例性能值，其特征在于考虑到所选参数（例如电路定时，电路功耗或电路面积）的电路的多个门实例级分量的性能 。 依赖于一组单元格实例性能值，确定电路中有问题的组件进行更换。 然后识别一组功能等效的候选组件。 相对于所选择的参数分析每个候选分量。 分析识别出最佳表现的候选组件。 然后将最佳执行的候选组件的实例替换为有问题的组件的网表，以改善电路的性能。

公开(公告)号：US5426591A

公开(公告)日：1995-06-20

申请号：US188292

申请日：1994-01-28

申请人： Arnold Ginetti ,  Mossaddeq Mahmood ,  Balmukund Sharma

发明人： Arnold Ginetti ,  Mossaddeq Mahmood ,  Balmukund Sharma

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell-based timing verifier that determines if a circuit meets specified timing requirements. Timing requirements are tested by computing a slack value for each node of the circuit at the component (macrocell) level, where the slack value represents the difference between the required arrival time of a signal at each circuit node and the computed worst case signal arrival time for the node. The output node having the most negative slack value is identified as a critical node. The HDL description of the circuit corresponding to the critical node is modified with a synthesis directive to substitute the original datapath cell with a better cell in order to improve the circuit's timing performance. The revised HDL description of the circuit is then re-synthesized. Improvements to the circuit may be repeated in this fashion until the circuit meets all timing constraints.

摘要翻译： 描述了用于自动修改电路的指定硬件描述语言（HDL）表征的计算机辅助设计系统和方法，以减少电路的关键路径上的信号延迟。 用逻辑合成器对指定的电路进行分析，该逻辑合成器包括基于小区的新颖的定时验证器，其确定电路是否满足规定的时序要求。 通过在组件（宏小区）级别计算电路的每个节点的松弛值来测试定时要求，其中松弛值表示每个电路节点处的信号的所需到达时间与计算的最坏情况信号到达时间之间的差 为节点。 具有最负的松弛值的输出节点被标识为关键节点。 用关键节点对应的电路的HDL描述用合成指令进行修改，以用更好的单元替换原始数据通路单元，以便提高电路的时序性能。 然后重新合成修订的电路的HDL描述。 可以以这种方式重复对电路的改进，直到电路满足所有时序约束。

公开(公告)号：US5541850A

公开(公告)日：1996-07-30

申请号：US245207

申请日：1994-05-17

申请人： Nels B. Vander Zanden ,  Mossaddeq Mahmood

发明人： Nels B. Vander Zanden ,  Mossaddeq Mahmood

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A set of circuit specifications including an internal memory structure is developed and then described in a hardware description language that is entered into a computer system. The circuit description is then synthesized on the computer to form a netlist to specify the circuit. From this netlist, an integrated circuit is produced on a semiconductor die, which is then packaged for use. A method for synthesizing a netlist from a hardware description including an internal memory structure includes converting the hardware description into an internal signal list, which contains an indication of the presence of an internal memory structure in the described circuit. For each memory structure indicated, synthesis is performed using a memory cell library, and compatibility between the hardware description for the circuit and the internal memory structure specified is determined. When compatibility is found, the internal memory structure is instantiated into the netlist for the circuit. A central processing unit (CPU) is connected to a keyboard used to input a hardware description of a circuit. Further included is a hardware description processor implemented on the CPU that creates mask generation data for use with a mask generator to form an integrated circuit. An internal memory structure as described in the hardware description of the circuit is thereby included in the circuit.

摘要翻译： 开发了包括内部存储器结构的一组电路规范，然后以输入到计算机系统的硬件描述语言来描述。 电路描述然后在计算机上合成以形成一个网表以指定电路。 从该网表中，在半导体管芯上产生集成电路，然后将其封装以供使用。 一种从包括内部存储器结构的硬件描述中合成网表的方法包括将硬件描述转换成内部信号列表，该内部信号列表包含所述电路中存在内部存储器结构的指示。 对于指示的每个存储器结构，使用存储器单元库执行合成，并且确定电路的硬件描述和指定的内部存储器结构之间的兼容性。 当发现兼容性时，将内部存储器结构实例化为电路的网表。 中央处理单元（CPU）连接到用于输入电路的硬件描述的键盘。 进一步包括在CPU上实现的硬件描述处理器，其创建用于与掩模发生器一起使用的掩模生成数据以形成集成电路。 因此，在电路的硬件描述中描述的内部存储器结构被包括在电路中。

公开(公告)号：US5841663A

公开(公告)日：1998-11-24

申请号：US528657

申请日：1995-09-14

申请人： Balmukund Sharma ,  Mossaddeq Mahmood ,  Arnold Ginetti

发明人： Balmukund Sharma ,  Mossaddeq Mahmood ,  Arnold Ginetti

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method and apparatus for designing circuits uses parameterized Hardware Description Language (HDL) modules stored in a library. A datapath synthesizer accesses the library and assigns values to parameters to form specific implementations of the parameterized HDL modules. The specific implementations of the parameterized HDL modules are used by the datapath synthesizer to implement an HDL circuit description. Each parameterized HDL module includes an entity description, a behavioral description, and an implementation description

摘要翻译： 用于设计电路的方法和装置使用存储在库中的参数化硬件描述语言（HDL）模块。 数据路径合成器访问库并为参数分配值以形成参数化HDL模块的特定实现。 数据路径合成器使用参数化HDL模块的具体实现来实现HDL电路描述。 每个参数化的HDL模块包括实体描述，行为描述和实现描述