公开(公告)号：US5726902A

公开(公告)日：1998-03-10

申请号：US482267

申请日：1995-06-07

申请人： Mossaddeq Mahmood ,  Mandalagiri Chandrasekhar ,  Arnold Ginetti ,  Balmukund K. Sharma

发明人： Mossaddeq Mahmood ,  Mandalagiri Chandrasekhar ,  Arnold Ginetti ,  Balmukund K. Sharma

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath cells and a gate library including primitive gate cells are provided, and a netlist is synthesized from the HDL description. The netlist is composed of datapath cells from the datapath library and primitive gate cells from the gate library. If a datapath cell instance in the netlist does not meet the timing constraints imposed by a user for the circuit, an alternative datapath cell instance can be substituted for that cell instance in a resynthesis and optimization step. An integrated circuit is preferably fabricated as specified by the resynthesized netlist. The netlist is preferably resynthesized multiple times in an iterative loop to optimize the netlist according to the constraints. The timing information for alternative cells used in the resynthesis of the netlist can be retrieved from a timing database in one embodiment. Timing information for datapath cells is stored in the timing database in a pre-characterization process, and the location of the timing information in the timing database is stored in a query database. In another embodiment, timing information for alternative datapath cells is calculated dynamically during the resynthesis process for optimizing the timing of a netlist.

摘要翻译： 一种用于表征集成电路设计和制造中数据通路的时序特性的方法和装置。 用于集成电路的一组电路规范以硬件描述语言（HDL）描述开发和描述。 提供包括数据路径单元和包括原始门单元的门库的数据路径库，并且从HDL描述合成网表。 网表由数据路径库的数据路径单元和门库的原始门单元组成。 如果网表中的数据路径小区实例不满足用户对该电路施加的时序约束，则可以在再合成和优化步骤中替代该数据路径小区实例来替换该小区实例。 优选地，由再合成网表规定制造集成电路。 网表优选在迭代循环中重新合成多次，以根据约束优化网表。 在一个实施例中，可以从定时数据库检索用于网表重新合成中的备选单元的定时信息。 用于数据通路单元的定时信息在预定制过程中存储在定时数据库中，定时数据库中定时信息​​的位置存储在查询数据库中。 在另一个实施例中，在用于优化网表的定时的再合成过程期间动态地计算替代数据路径小区的定时信息。

公开(公告)号：US5764525A

公开(公告)日：1998-06-09

申请号：US442290

申请日：1995-05-16

申请人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Arnold Ginetti ,  Francois Silve

发明人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Arnold Ginetti ,  Francois Silve

IPC分类号： G06F17/50 ,  G06F15/00

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

摘要翻译： 描述一种设计电路的方法。 生成电路的网表。 然后执行网表的分析以产生一组细胞实例性能值，其特征在于考虑到所选参数（例如电路定时，电路功耗或电路面积）的电路的多个门实例级分量的性能 。 依赖于一组单元格实例性能值，确定电路中有问题的组件进行更换。 然后识别一组功能等效的候选组件。 相对于所选择的参数分析每个候选分量。 分析识别出最佳表现的候选组件。 然后将最佳执行的候选组件的实例替换为有问题的组件的网表，以改善电路的性能。

公开(公告)号：US5519627A

公开(公告)日：1996-05-21

申请号：US339928

申请日：1994-11-15

申请人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Christopher H. Kingsley

发明人： Mossaddeq Mahmood ,  Balmukund K. Sharma ,  Christopher H. Kingsley

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and control logic. The control logic is implemented in standard cells or gate arrays using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath elements, including both structural components and computational components, where some of the computational components are complex circuits having multiple, parallel outputs. Each computational component has associated therewith a set of one or more datapath expressions performed thereby. The received HDL circuit specification is converted into circuit data structures representing the circuit's datapath expressions and structural components. The datapath synthesizer locates all datapath elements in said library matching each such datapath expression and structural component. Then an optimizer determines which datapath expressions can be "combined", or performed by a single library element, so as to reduce the circuit layout area used. The optimizer can combine multiple datapath expressions so as to use datapath circuit elements having multiple parallel outputs. Finally, one library element is selected for each datapath expression, or combined expression, on the basis of circuit area, speed, power or other optimization criteria. Then the connections between the selected circuit components are computed and the resulting circuit is output in the form of a circuit netlist.

摘要翻译： 数据路径电路合成器将HDL电路规范转换为电路网表。 指定电路的行为描述分为两个不同的部分：数据路径逻辑和控制逻辑。 控制逻辑使用逻辑合成器在标准单元或门阵列中实现。 数据路径逻辑使用具有数据路径元素库（包括结构组件和计算组件）的数据路径合成器进行最佳合成，其中一些计算组件是具有多个并行输出的复杂电路。 每个计算组件都具有与之相关的一组一个或多个数据路径表达式。 接收的HDL电路规范被转换成表示电路的数据路径表达式和结构组件的电路数据结构。 数据路径合成器定位所有库中的所有数据路径元素，以匹配每个这样的数据路径表达式和结构组件。 然后，优化器确定哪个数据路径表达式可以“组合”，或由单个库元素执行，以便减少使用的电路布局面积。 优化器可以组合多个数据路径表达式，以便使用具有多个并行输出的数据通路电路元件。 最后，基于电路面积，速度，功率或其他优化标准，为每个数据路径表达式或组合表达式选择一个库元素。 然后计算所选择的电路部件之间的连接，并且所得到的电路以电路网表的形式输出。

公开(公告)号：US5491640A

公开(公告)日：1996-02-13

申请号：US272205

申请日：1994-07-08

申请人： Balmukund K. Sharma ,  Mossaddeq Mahmood

发明人： Balmukund K. Sharma ,  Mossaddeq Mahmood

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5045

摘要： A method for fabricating an integrated circuit includes the steps of: (a) developing a set of circuit specifications for an integrated circuit; (b) encoding the set of circuit specifications in a hardware description language (HDL); (c) synthesizing a netlist including a sequential datapath with a datapath synthesizer from the HDL; and (d) fabricating an integrated circuit as specified by the netlist. A method for datapath synthesis includes the steps of: (a) providing a datapath library including sequential components and combinational components; (b) developing a set of circuit specifications for an integrated circuit; (c) encoding the set of circuit specifications in a HDL; (d) developing a number of IC expression trees derived from the HDL; (e) matching the IC expression trees with library expression trees derived from the datapath library to provide a map of matches; and (f) synthesizing according to the map to create a datapath netlist including both sequential datapaths and combinational datapaths. A datapath synthesizer includes a digital processor, memory coupled to the digital processor, and a datapath library stored in the memory. An input device is used to input a HDL description of circuit specifications into memory, and an IC expression generator develops a number of IC expression trees from the HDL. A matcher compares the plurality of IC expression trees with library expression trees derived from the datapath library to provide a map of matches, and a synthesizer provides a netlist including both sequential datapaths and combinational datapaths according to the map.

摘要翻译： 一种用于制造集成电路的方法包括以下步骤：（a）开发用于集成电路的一组电路规范; （b）以硬件描述语言（HDL）对该组电路规范进行编码; （c）从HDL合成包括数据通路合成器的顺序数据路径的网表; 和（d）制造由网表规定的集成电路。 一种用于数据通路合成的方法包括以下步骤：（a）提供包括顺序分量和组合分量的数据路径库; （b）为集成电路开发一套电路规范; （c）以HDL编码该组电路规格; （d）开发一些源自HDL的IC表达树; （e）将IC表达式树与从数据路径库派生的库表达式树匹配以提供匹配的映射; 和（f）根据地图合成以创建包括顺序数据路径和组合数据路径两者的数据路径网表。 数据路径合成器包括数字处理器，耦合到数字处理器的存储器和存储在存储器中的数据路径库。 输入装置用于将电路规格的HDL描述输入到存储器中，并且IC表达式生成器从HDL开发许多IC表达树。 匹配器将多个IC表达式树与从数据路径库导出的库表达式树进行比较，以提供匹配映射，并且合成器根据地图提供包括顺序数据路径和组合数据路径的网表。

公开(公告)号：US20080201254A1

公开(公告)日：2008-08-21

申请号：US11709670

申请日：2007-02-21

申请人： Balmukund K. Sharma ,  Alan F. Abola

发明人： Balmukund K. Sharma ,  Alan F. Abola

IPC分类号： G06Q40/00

CPC分类号： G06Q30/06 ,  G06Q10/06 ,  G06Q40/04

摘要： In preferred embodiments, a supplier enablement method including the steps of identifying and assessing capabilities of potential suppliers; engaging (pre-qualifying) selected potential suppliers; and enabling automated transactions (e.g., purchase orders and billing) between a buyer and each engaged supplier. Preferred embodiments of the method implement supplier enablement in three phases: supplier selection by a buyer; activation of each selected supplier; and management of relationships between the buyer and each selected supplier. Preferably, each phase has three subphases: the supplier selection phase includes identification of potential suppliers; assessment of their capabilities; and engagement of selected potential suppliers; the activation phase includes registration of each engaged supplier; content provision; and enablement of transaction business documents (e.g., purchase orders) for use by each buyer and engaged supplier; and the management phase includes collaboration operations, compliance operations, and improvement operations. Other aspects are processors programmed to perform one or more individual steps of any embodiment of the method, and computer readable media which store code for implementing any embodiment of the method.

摘要翻译： 在优选实施例中，供应商启用方法包括以下步骤：识别和评估潜在供应商的能力; 参与（预选）选定的潜在供应商; 并允许买方和每个从业供应商之间进行自动交易（例如，采购订单和计费）。 该方法的优选实施例分三个阶段实施供应商实施：供应商由买方选择; 激活每个选定的供应商; 并对买方和每个选定的供应商之间的关系进行管理。 优选地，每个阶段具有三个子阶段：供应商选择阶段包括潜在供应商的识别; 评估其能力; 选定潜在供应商的参与; 激活阶段包括每个从业供应商的注册; 内容规定; 以及启用交易业务单据（例如采购订单）供每个买方和被聘用的供应商使用; 管理阶段包括协作运作，合规运营和改进运营。 其他方面是被编程为执行该方法的任何实施例的一个或多个单独步骤的处理器和存储用于实现该方法的任何实施例的代码的计算机可读介质。

公开(公告)号：US5854926A

公开(公告)日：1998-12-29

申请号：US376491

申请日：1995-01-23

申请人： Christopher H. Kingsley ,  Balmukund K. Sharma

发明人： Christopher H. Kingsley ,  Balmukund K. Sharma

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals. The symbolic hardware implementations for each net can then be optimized using well-known techniques, and a netlist generated therefrom for purposes of creating masks for manufacturing the circuit. The invention can be easily implemented within known symbolic simulator routines already capable of synthesizing level-sensitive behavior using combinational logic.

摘要翻译： 公开了一种用于从电路的HDL描述检测边缘敏感行为的方法和装置，并且推断出具有异步设置和清除输入的广义边缘触发D型触发器的该行为的硬件实现。 本发明检测来自定向非循环图（DAGS）的边缘敏感行为，其表示电路的各个信号网络受电路HDL描述中定义的每个过程的影响。 然后，本发明修改每个DAG以推断控制广义触发器以模拟由DAG表示的网络的行为所需的异步控制表达式和数据输入表达式。 然后，本发明使用D型触发器和产生推断的控制信号所必需的任何组合逻辑来创建网络行为的符号硬件实现。 然后可以使用众所周知的技术来优化每个网络的符号硬件实现，以及为此创建用于制造用于制造电路的掩模的网表。 本发明可以容易地在已经能够使用组合逻辑合成水平敏感行为的已知符号仿真程序中实现。