公开(公告)号：US20040099878A1

公开(公告)日：2004-05-27

申请号：US10304493

申请日：2002-11-26

Applicant: Motorola, Inc.

Inventor： Wen Ling M. Huang ,  Sushil Bharatan ,  Carl Kyono ,  David J. Monk ,  Kun-Hin To ,  Pamela J. Welch

IPC: H01L029/74 ,  H01L031/111 ,  H01L029/76 ,  H01L029/94

CPC classification number: H01L27/0928 ,  H01L21/761 ,  H01L21/84 ,  H01L27/1203

Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).

Abstract translation: 通过用于片上系统（SOC）（2）应用的半导体衬底降低信号串扰的结构，从而有助于将数字电路块（6）和模拟电路块（8）集成到单个IC上。 通过将分离的井（10），（12），（16）和（20）中的各种数字电路块（6）和模拟电路块（8）策略性​​地定位在多个数字电路块（6）和（20）上，通过衬底（4）的交叉电路相互作用被减少。 电阻衬底（4）。 然后，这些阱结构（10），（12），（16）和（20）被图案化的低电阻率层（22）和任选的沟槽区域（24）包围。 图案化的低电阻率区域（22）形成在阱（10）和（12）下方，并且用作低电阻AC接地层。 该低电阻率区域（22）收集在数字电路块（6）和模拟电路块（8）之间传播的噪声信号。