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    SOI polysilicon trench refill perimeter oxide anchor scheme
    2.
    发明申请
    SOI polysilicon trench refill perimeter oxide anchor scheme 有权
    SOI多晶硅沟槽填充周边氧化物锚定方案

    公开(公告)号：US20040048410A1

    公开(公告)日：2004-03-11

    申请号：US10238062

    申请日：2002-09-09

    Applicant: Motorola Inc.

    Inventor： Gary J. O'Brien ,  David J. Monk

    IPC: H01L021/00

    CPC classification number: B81C1/00039 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/033

    Abstract: A method for creating a MEMS structure is provided. In accordance with the method, a substrate (53) is provided having a sacrificial layer (55) disposed thereon and having a layer of silicon (57) disposed over the sacrificial layer. A first trench (59) is created which extends through the silica layer and the sacrificial layer and which separates the sacrificial layer into a first region (61) enclosed by the first trench and a second region (63) exterior to the first trench. A first material (65) is deposited into the first trench such that the first material fills the first trench to a depth at least equal to the thickness of the sacrificial layer. A second trench (71) is created exterior to the first trench which extends through at least the silicon layer and exposes at least a portion of the second region of the sacrificial layer. The second region of the sacrificial layer is contacted, by way of the second trench, with a chemical etching solution adapted to etch the sacrificial layer, said etching solution being selective to the first material.

    Abstract translation: 提供了一种用于产生MEMS结构的方法。 根据该方法，提供了具有设置在其上的牺牲层（55）并且具有设置在牺牲层上方的硅层（57）的衬底（53）。 产生第一沟槽（59），其延伸穿过二氧化硅层和牺牲层，并且将牺牲层分离成由第一沟槽包围的第一区域（61）和第一沟槽外部的第二区域（63）。 第一材料（65）沉积到第一沟槽中，使得第一材料将第一沟槽填充到至少等于牺牲层厚度的深度。 在第一沟槽的外部产生第二沟槽（71），其延伸穿过至少硅层并暴露牺牲层的第二区域的至少一部分。 牺牲层的第二区域通过第二沟槽与适于蚀刻牺牲层的化学蚀刻溶液接触，所述蚀刻溶液对第一材料是选择性的。

    Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
    3.
    发明申请
    Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications 有权
    通过半导体衬底降低信号串扰的结构，用于片上系统应用

    公开(公告)号：US20040099878A1

    公开(公告)日：2004-05-27

    申请号：US10304493

    申请日：2002-11-26

    Applicant: Motorola, Inc.

    Inventor： Wen Ling M. Huang ,  Sushil Bharatan ,  Carl Kyono ,  David J. Monk ,  Kun-Hin To ,  Pamela J. Welch

    IPC: H01L029/74 ,  H01L031/111 ,  H01L029/76 ,  H01L029/94

    CPC classification number: H01L27/0928 ,  H01L21/761 ,  H01L21/84 ,  H01L27/1203

    Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).

    Abstract translation: 通过用于片上系统（SOC）（2）应用的半导体衬底降低信号串扰的结构，从而有助于将数字电路块（6）和模拟电路块（8）集成到单个IC上。 通过将分离的井（10），（12），（16）和（20）中的各种数字电路块（6）和模拟电路块（8）策略性​​地定位在多个数字电路块（6）和（20）上，通过衬底（4）的交叉电路相互作用被减少。 电阻衬底（4）。 然后，这些阱结构（10），（12），（16）和（20）被图案化的低电阻率层（22）和任选的沟槽区域（24）包围。 图案化的低电阻率区域（22）形成在阱（10）和（12）下方，并且用作低电阻AC接地层。 该低电阻率区域（22）收集在数字电路块（6）和模拟电路块（8）之间传播的噪声信号。

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