公开(公告)号：US07030022B2

公开(公告)日：2006-04-18

申请号：US10655423

申请日：2003-09-04

Applicant: Mu-kyoung Jung ,  Kyung-tae Lee

Inventor： Mu-kyoung Jung ,  Kyung-tae Lee

IPC: H01L21/302

CPC classification number: H01L21/76838 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of manufacturing a semiconductor device having a first region, in which a capacitance component is a dominant cause of a RC delay, and a second region, in which a resistance component is a dominant cause of a RC delay. The method comprises performing a first etching process to an insulating layer formed on a semiconductor substrate, so that a first trench having a first thickness and a second trench having the first thickness are formed in the first region and the second region, respectively; performing a second etching process to the second trench, so that a third trench having a second thickness thicker than the first thickness is formed in the second region; filling the first trench and the third trench with a metal layer; and removing portions of the metal layer, so that a first metal interconnection and a second metal interconnection are formed inside of the first trench and the third trench, respectively.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件具有其中电容分量是RC延迟的主要原因的第一区域和其中电阻分量是RC延迟的主要原因的第二区域。 该方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻处理，使得具有第一厚度的第一沟槽和具有第一厚度的第二沟槽分别形成在第一区域和第二区域中; 对所述第二沟槽进行第二蚀刻处理，使得在所述第二区域中形成具有比所述第一厚度更厚的第二厚度的第三沟槽; 用金属层填充第一沟槽和第三沟槽; 以及去除金属层的部分，使得分别在第一沟槽和第三沟槽内部形成第一金属互连和第二金属互连。