公开(公告)号：US07030022B2

公开(公告)日：2006-04-18

申请号：US10655423

申请日：2003-09-04

Applicant: Mu-kyoung Jung ,  Kyung-tae Lee

Inventor： Mu-kyoung Jung ,  Kyung-tae Lee

IPC: H01L21/302

CPC classification number: H01L21/76838 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of manufacturing a semiconductor device having a first region, in which a capacitance component is a dominant cause of a RC delay, and a second region, in which a resistance component is a dominant cause of a RC delay. The method comprises performing a first etching process to an insulating layer formed on a semiconductor substrate, so that a first trench having a first thickness and a second trench having the first thickness are formed in the first region and the second region, respectively; performing a second etching process to the second trench, so that a third trench having a second thickness thicker than the first thickness is formed in the second region; filling the first trench and the third trench with a metal layer; and removing portions of the metal layer, so that a first metal interconnection and a second metal interconnection are formed inside of the first trench and the third trench, respectively.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件具有其中电容分量是RC延迟的主要原因的第一区域和其中电阻分量是RC延迟的主要原因的第二区域。 该方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻处理，使得具有第一厚度的第一沟槽和具有第一厚度的第二沟槽分别形成在第一区域和第二区域中; 对所述第二沟槽进行第二蚀刻处理，使得在所述第二区域中形成具有比所述第一厚度更厚的第二厚度的第三沟槽; 用金属层填充第一沟槽和第三沟槽; 以及去除金属层的部分，使得分别在第一沟槽和第三沟槽内部形成第一金属互连和第二金属互连。

公开(公告)号：US20050127496A1

公开(公告)日：2005-06-16

申请号：US10978619

申请日：2004-11-01

Applicant: Ki-hyoun Kwon ,  Kyung-tae Lee ,  Seong-ho Liu ,  Yoon-hae Kim

Inventor： Ki-hyoun Kwon ,  Kyung-tae Lee ,  Seong-ho Liu ,  Yoon-hae Kim

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/12 ,  H01L21/4763

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/30105

Abstract: A bonding pad in a semiconductor device can include a conductive plug pattern on a conductive layer, where the conductive layer includes a conductive material and a dummy pattern surrounded by the conductive material. Related methods are also disclosed.

Abstract translation: 半导体器件中的焊盘可以包括在导电层上的导电插塞图案，其中导电层包括导电材料和由导电材料包围的虚拟图案。 还公开了相关方法。

公开(公告)号：US06492260B1

公开(公告)日：2002-12-10

申请号：US09447466

申请日：1999-11-22

Applicant: Young-wug Kim ,  Kyung-tae Lee

Inventor： Young-wug Kim ,  Kyung-tae Lee

IPC: H01L214763

CPC classification number: H01L21/7684 ,  H01L21/76834

Abstract: A method of forming damascene wiring without dishing and erosion employs a dummy layer to slow or delay polishing in selected regions and thereby prevent dishing and erosion of the damascene wiring. The dummy layer is above wide damascene regions and areas containing closely packed damascene regions. Therefore, non-uniform sheet resistance of the damascene metal wiring and electro-migration due to an increase in the local current density of the metal wiring can be prevented.

Abstract translation: 在不进行凹陷和侵蚀的情况下形成镶嵌布线的方法使用虚拟层来减缓或延迟所选区域中的抛光，从而防止镶嵌布线的凹陷和侵蚀。 虚拟层位于宽大的镶嵌区域和包含紧密堆积的镶嵌区域的区域之上。 因此，可以防止由金属布线的局部电流密度的增加引起的非镶嵌金属布线的非均匀的薄层电阻和电迁移。

公开(公告)号：US20050029010A1

公开(公告)日：2005-02-10

申请号：US10891062

申请日：2004-07-15

Applicant: Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

Inventor： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Abstract translation: 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

公开(公告)号：US07579643B2

公开(公告)日：2009-08-25

申请号：US11706972

申请日：2007-02-16

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

Abstract translation: 电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。 第一电极可以包括至少一个第一电极分支。 第二电极可面向第一电极并且包括至少一个第二电极分支。 低电介质层可以形成在第一电极分支和第二电极分支之间。 高电介质层可以形成在第一电极分支和第二电极分支之间。 高介电层可以具有比低介电层更高的介电常数。

公开(公告)号：US07229875B2

公开(公告)日：2007-06-12

申请号：US10688077

申请日：2003-10-16

Applicant: Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

Inventor： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC: H01L21/8234

CPC classification number: H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract translation: 本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US07220652B2

公开(公告)日：2007-05-22

申请号：US10901239

申请日：2004-07-29

Applicant: Yoon-hae Kim ,  Kyung-tae Lee ,  Seong-ho Liu

Inventor： Yoon-hae Kim ,  Kyung-tae Lee ,  Seong-ho Liu

IPC: H01L21/20

CPC classification number: H01L28/40 ,  H01L28/75

Abstract: A method of manufacturing a MIM capacitor and a interconnecting structure using a damascene process. The MIM capacitor and the first interconnecting structure can be formed at equal depths.

Abstract translation: 使用镶嵌工艺制造MIM电容器和互连结构的方法。 MIM电容器和第一互连结构可以以相等的深度形成。

公开(公告)号：US06746951B2

公开(公告)日：2004-06-08

申请号：US09906303

申请日：2001-07-16

Applicant: Seong-ho Liu ,  Kyung-tae Lee

Inventor： Seong-ho Liu ,  Kyung-tae Lee

IPC: H01L214763

CPC classification number: H01L24/05 ,  H01L21/7684 ,  H01L23/4827 ,  H01L24/03 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05679 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/30105 ,  H01L2224/05552

Abstract: A bond pad of a semiconductor device capable of restraining dishing and having improved conductivity by a damascene technique using a copper pattern, includes first and second copper patterns of irregular lattice models, first and second dielectric layer patterns to connect the first and second copper patterns in the vertical direction, a line connection structure horizontally connecting the first and second copper patterns, and a conductivity improving layer formed on the first and second copper patterns. Dishing generated in planarizing the first and second copper patterns by a damascene technique can be restrained due to the first and second copper patterns of the lattice models. Also, the conductivity property of the bond pad can be improved by connecting the first and second copper patterns horizontally and in the vertical direction and further forming the conductivity improving layer on the first and second copper patterns.

Abstract translation: 能够通过使用铜图案的镶嵌技术来抑制凹陷并具有改善的导电性的半导体器件的接合焊盘包括不规则晶格模型的第一和第二铜图案，用于连接第一和第二铜图案的第一和第二电介质层图案 垂直方向，水平连接第一和第二铜图案的线连接结构，以及形成在第一和第二铜图案上的导电率改善层。 由于晶格模型的第一和第二铜图案，可以通过镶嵌技术对第一和第二铜图案进行平坦化产生的抛光进行限制。 此外，可以通过在第一和第二铜图案上水平和垂直方向上连接第一和第二铜图案并进一步形成导电率改进层来提高接合焊盘的导电性。

公开(公告)号：US20070200159A1

公开(公告)日：2007-08-30

申请号：US11706972

申请日：2007-02-16

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

IPC: H01L29/94

CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

Abstract translation: 电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。 第一电极可以包括至少一个第一电极分支。 第二电极可面向第一电极并且包括至少一个第二电极分支。 低电介质层可以形成在第一电极分支和第二电极分支之间。 高电介质层可以形成在第一电极分支和第二电极分支之间。 高介电层可以具有比低介电层更高的介电常数。

公开(公告)号：US20070145452A1

公开(公告)日：2007-06-28

申请号：US11684865

申请日：2007-03-12

Applicant: Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

Inventor： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

IPC: H01L29/94

CPC classification number: H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

Abstract translation: 集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。 介电层位于下电极层上，电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间介电层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。