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    JAVA HARDWARE ACCELERATOR USING MICROCODE ENGINE
    5.
    发明申请
    JAVA HARDWARE ACCELERATOR USING MICROCODE ENGINE 失效
    JAVA硬件加速器使用微型发动机

    公开(公告)号：US20070118724A1

    公开(公告)日：2007-05-24

    申请号：US11538362

    申请日：2006-10-03

    申请人： Mukesh Patel

    发明人： Mukesh Patel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30174 ,  G06F9/3879

    摘要： A hardware Java accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.

    摘要翻译： 硬件Java加速器由解码级和微码级组成。 分解为解码和微码级允许解码级实现指令级并行性，而微代码级允许将单个Java字节码转换为多个本机指令。 提供重发缓冲器，其存储转换的指令，并且当系统从中断返回时重新发行它们。 以这种方式，硬件加速器不必在中断时被刷新。 还使用本机PC显示器。 当本机PC在特定范围内时，硬件加速器能够将Java字节码转换为本地指令。 当本地PC超出该范围时，硬件加速器被禁用，并且CPU对从存储器获得的本地指令进行操作。

    Test ramp for testing microactuators used in a multi-head disk drive
    6.
    发明授权
    Test ramp for testing microactuators used in a multi-head disk drive 失效
    用于测试多头磁盘驱动器中使用的微动作器的测试斜坡

    公开(公告)号：US08499652B1

    公开(公告)日：2013-08-06

    申请号：US12764800

    申请日：2010-04-21

    申请人： Gregory Tran ,  Yanning Liu ,  Sivabalan Ganisen ,  Mukesh Patel

    发明人： Gregory Tran ,  Yanning Liu ,  Sivabalan Ganisen ,  Mukesh Patel

    IPC分类号： G01N19/00

    CPC分类号： G11B19/048

    摘要： A test ramp is disclosed comprising a plurality of planar surfaces, wherein each planar surface comprises at least one impediment. Each impediment is offset along a planar axis from the other impediments, and each impediment is operable to contact part of a respective actuator arm of a disk drive in order to excite a microactuator coupled to the actuator arm.

    摘要翻译： 公开了包括多个平面表面的测试斜坡，其中每个平面表面包括至少一个障碍物。 每个障碍物沿着平面轴线与其他障碍物偏移，并且每个障碍物可操作以接触盘驱动器的相应致动器臂的一部分，以便激励耦合到致动器臂的微致动器。

    Method and system for coupling a stack based processor to register based functional unit
    7.
    发明授权
    Method and system for coupling a stack based processor to register based functional unit 失效
    用于将基于堆栈的处理器耦合到基于寄存器的功能单元的方法和系统

    公开(公告)号：US6088786A

    公开(公告)日：2000-07-11

    申请号：US884255

    申请日：1997-06-27

    申请人： Gary Feierbach ,  Mukesh Patel

    发明人： Gary Feierbach ,  Mukesh Patel

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F15/00

    CPC分类号： G06F9/30134 ,  G06F15/7832 ,  G06F9/3879

    摘要： A microprocessor capable of performing multimedia and non-multimedia operations provided a plurality of stack based instructions is provided. The microprocessor includes a stack processor coupled to a stack capable of storing values, a register processor coupled to a register file capable of storing values, and a copy-unit having a first port coupled to the stack and a second port coupled to the register file being configured to copy data between the register file and the stack. The microprocessor also includes logic coupled to receive the plurality of stack based instructions from memory, cache, or other storage devices coupled to the microprocessor. The logic is configured to determine which of the plurality of stack based instructions are regular stack instructions and which of the plurality of stack based instructions are extended stack instructions. A stack decoder having a first port coupled to the logic and a second port coupled to the stack processor is configured to decode the regular stack instructions and provide control signals to the stack processor. A copy-unit decoder having a first port coupled to the logic and a second port coupled to the copy-unit is configured to decode extended stack instructions and provide control signals to the copy-unit. Further, a register processor decoder having a first port coupled to the logic and a second port coupled to the register processor is configured to decode extended stack instructions and provide the decoded extended stack instructions to the register processor.

    摘要翻译： 提供了能够执行多媒体和非多媒体操作的微处理器，提供了多个基于堆栈的指令。 微处理器包括耦合到能够存储值的堆栈的堆栈处理器，耦合到能够存储值的寄存器文件的寄存器处理器，以及具有耦合到堆栈的第一端口的复制单元和耦合到寄存器堆的第二端口 被配置为在寄存器文件和堆栈之间复制数据。 微处理器还包括耦合以从存储器，高速缓存或耦合到微处理器的其它存储设备接收多个基于堆栈的指令的逻辑。 逻辑被配置为确定多个基于堆栈的指令中的哪一个是常规堆栈指令，以及多个基于堆栈的指令中的哪一个是扩展堆栈指令。 具有耦合到逻辑的第一端口和耦合到堆栈处理器的第二端口的堆栈解码器被配置为对常规栈指令进行解码，并向堆栈处理器提供控制信号。 具有耦合到逻辑的第一端口和耦合到复制单元的第二端口的复制单元解码器被配置为解码扩展堆栈指令并向复制单元提供控制信号。 此外，具有耦合到逻辑的第一端口和耦合到寄存器处理器的第二端口的寄存器处理器解码器被配置为解码扩展堆栈指令并将解码的扩展堆栈指令提供给寄存器处理器。

    Quick-drying coating compositions
    8.
    发明授权
    Quick-drying coating compositions 失效
    快干涂料组合物

    公开(公告)号：US6051242A

    公开(公告)日：2000-04-18

    申请号：US876347

    申请日：1997-06-16

    申请人： Mukesh Patel ,  Larry W. Steffier

    发明人： Mukesh Patel ,  Larry W. Steffier

    IPC分类号： A61K8/35 ,  A61K8/38 ,  A61K8/73 ,  A61K8/81 ,  A61Q3/02 ,  A61K6/00 ,  A61K7/00 ,  A61K7/04

    CPC分类号： A61K8/35 ,  A61K8/38 ,  A61K8/731 ,  A61K8/8152 ,  A61Q3/02

    摘要： Quick drying coating compositions, preferably but not exclusively for application to natural or artificial nails are provided. The quick-drying coating composition comprises a base or lacquer component and an optional pigment component. The base component can dry in less than about 70 seconds under ambient conditions, yet is free of undesirable solvents and components such as acetone, toluene, chlorinated hydrocarbons, and formaldehyde-containing resins. The base component includes film-forming polymers, a monomer component compatible with the polymers, and a free radical source.

    摘要翻译： 提供快速干燥的涂料组合物，优选但不排他地用于应用于天然或人造指甲。 快干涂料组合物包含碱或漆组分和任选的颜料组分。 基础组分可在环境条件下在少于约70秒内干燥，但不含不需要的溶剂和组分如丙酮，甲苯，氯化烃和含甲醛的树脂。 基础组分包括成膜聚合物，与聚合物相容的单体组分和自由基源。

    Processor complex for executing multimedia functions
    9.
    发明授权
    Processor complex for executing multimedia functions 失效
    用于执行多媒体功能的处理器

    公开(公告)号：US5892966A

    公开(公告)日：1999-04-06

    申请号：US884257

    申请日：1997-06-27

    申请人： Bruce E. Petrick ,  Mukesh Patel

    发明人： Bruce E. Petrick ,  Mukesh Patel

    IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F13/40

    CPC分类号： G06F9/3879 ,  Y10S707/99945 ,  Y10S707/99948

    摘要： A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism. A main memory device is also coupled to the hardware processor over bidirectional port and coupled to the multimedia processor over a second bidirectional port. This arrangement allows the hardware processor and the coprocessor to share main memory and load separate instruction streams from main memory.

    摘要翻译： 提供了一种包括耦合到多媒体协处理器的硬件处理器的计算机处理器复合体。 除了在MPEG音频和视频中使用的多媒体指令流之外，该计算机处理器复合体能够分开地处理非多媒体指令流。 计算机处理器复合体包括可见寄存器集合，其包括用于程序计数器和数据指针的寄存器。 程序计数器用于将地址保存在多媒体指令所在的存储器中，数据指针指示对应于这些多媒体指令的数据位于存储器中的位置。 硬件处理器耦合到可见寄存器组上的第一双向端口，并且多媒体协处理器耦合到可见寄存器组上的第二双向端口。 双向端口允许硬件处理器和协处理器通常使用基于中断的通信机制交换数据和状态信息。 主存储器件还通过双向端口耦合到硬件处理器，并通过第二双向端口耦合到多媒体处理器。 这种布置允许硬件处理器和协处理器共享主存储器并从主存储器加载分离的指令流。

    Java Virtual Machine hardware for RISC and CISC processors
    10.
    发明申请
    Java Virtual Machine hardware for RISC and CISC processors 失效
    用于RISC和CISC处理器的Java虚拟机硬件

    公开(公告)号：US20060200801A1

    公开(公告)日：2006-09-07

    申请号：US11353432

    申请日：2006-02-14

    申请人： Mukesh Patel ,  Jay Kamdar ,  V. Ranganath

    发明人： Mukesh Patel ,  Jay Kamdar ,  V. Ranganath

    IPC分类号： G06F9/44

    CPC分类号： G06F9/30174 ,  G06F8/443 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/3879 ,  G06F9/44521

    摘要： A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes. The Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions. The combination of the Java hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java programs for use in commercial appliances.

    摘要翻译： 提供硬件Java加速器来实现硬件中的Java虚拟机的部分，以加速系统对Java字节码的操作。 Java硬件加速器最好将Java字节码转换成本机CPU指令。 Java硬件加速器和CPU的组合提供了一种嵌入式解决方案，从而导致运行用于商业设备的Java程序的廉价系统。