公开(公告)号：US07251797B2

公开(公告)日：2007-07-31

申请号：US10994858

申请日：2004-11-22

申请人： Murat R. Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran V. Panda ,  Vladimir P. Zolotov

发明人： Murat R. Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran V. Panda ,  Vladimir P. Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

摘要翻译： 用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。 有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何 部分316对受害者时机的影响超出受害者定时窗口。 有效的延迟时间用于调整受害者计时窗口。 基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u 1）（613,625）。

公开(公告)号：US20060112359A1

公开(公告)日：2006-05-25

申请号：US10994858

申请日：2004-11-22

申请人： Murat Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran Panda ,  Vladimir Zolotov

发明人： Murat Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran Panda ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

摘要翻译： 用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。 有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何 部分316对受害者时机的影响超出受害者定时窗口。 有效的延迟时间用于调整受害者计时窗口。 基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u1）（613,625）。

公开(公告)号：US06799153B1

公开(公告)日：2004-09-28

申请号：US09553271

申请日：2000-04-20

申请人： Supamas Sirichotiyakul ,  David T. Blaauw ,  Chanhee Oh ,  Vladimir P. Zolotov ,  Rafi Levy

发明人： Supamas Sirichotiyakul ,  David T. Blaauw ,  Chanhee Oh ,  Vladimir P. Zolotov ,  Rafi Levy

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor. Accurate delay characterization provides for design engineers an accurate description of the worst case and best case scenarios of the integrated circuit or microprocessor that is needed for various applications such as the integration of the integrated circuit and microprocessor into a larger system.

摘要翻译： 对集成电路和其他微处理器应用执行交叉耦合延迟特性的解决方案。 本发明在各种时间适当地对各种配置的集成电路建模，以适应与驱动器电路相关联的非线性以及集成电路内的网络之间的不期望的电容耦合，特别是那些位于彼此非常接近并且产生有害的 司机过渡的影响从低到高，从高到低。 本发明提供了一种计算上有效的解决方案来执行微处理器内各个转换操作的加速和减慢的延迟表征。 精确的延迟表征为设计工程师提供了对于各种应用所需的集成电路或微处理器的最坏情况和最佳情况的精确描述，例如将集成电路和微处理器集成到更大的系统中。