公开(公告)号：US20230192480A1

公开(公告)日：2023-06-22

申请号：US18066755

申请日：2022-12-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Altti TORKKELI ,  Hidetoshi FUJII

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00968 ,  B81B3/001 ,  B81C2201/0133 ,  B81C2201/0178

Abstract: A method for manufacturing a structural layer in a silicon wafer is provide. The silicon wafer has at least two areas vertically recessed to at least two recess depths, with the first recess depth being greater than the second recess depth. The method includes forming a silicon dioxide pattern, a mask layer and a silicon dioxide pad layer, etching the structural layer in a main LOCOS oxidation process, and removing the formed layers exposing the recessed structural layer. The manufactured structural layer has a bump structure with the recess depth smaller than the second recess depth, and the recessed area has no edge steps.

公开(公告)号：US20210002131A1

公开(公告)日：2021-01-07

申请号：US17003703

申请日：2020-08-26

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Hidetoshi FUJII

IPC: B81C1/00

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

公开(公告)号：US20200168465A1

公开(公告)日：2020-05-28

申请号：US16675951

申请日：2019-11-06

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Hidetoshi FUJII

IPC: H01L21/308 ,  H01L21/306

Abstract: A method for manufacturing recessed micromechanical structures in a wafer. A first etching mask and a second etching mask are patterned on the horizontal face of the wafer. The second etching mask defines at least one recess area and the first etching mask defines at least one etch-control area within the at least one recess area. The placement, number and dimensions of the etch-control areas influence the vertical etch rate of the recessed structure. Adjacent structures can be etched to different recess depths by selecting suitable etch-control areas.

公开(公告)号：US20180346326A1

公开(公告)日：2018-12-06

申请号：US15981327

申请日：2018-05-16

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Hidetoshi FUJII

IPC: B81C1/00

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.