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公开(公告)号：US20230308059A1
公开(公告)日：2023-09-28
申请号：US18189402
申请日：2023-03-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yuri HONDA , Hideyuki SATOU , Satoshi TANAKA
CPC classification number: H03F3/211 , H03F1/0222 , H03F2200/451
Abstract: A power amplifier circuit includes a first amplification element having an output terminal and amplifying a harmonic signal input to an input terminal, a second amplification element having an output terminal and amplifying a harmonic signal input to an input terminal, a bias circuit that supplies a bias to each of the input terminal of the first amplification element and the second amplification element, a first resistance element electrically connected to the output terminal of the first amplification element, and a second resistance element electrically connected to the output terminal of the second amplification element and electrically connected to the other end of the first resistance element in series, the bias circuit is electrically connected to a connection point in a portion in which the other end of the first resistance element and the other end of the second resistance element are electrically connected in series.
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公开(公告)号：US20200169232A1
公开(公告)日：2020-05-28
申请号：US16694025
申请日：2019-11-25
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi GOTO , Hideyuki SATOU , Satoshi TANAKA
Abstract: A power amplifying circuit includes an amplifier that amplifies a radio-frequency signal and a bypass capacitor section connected to a power supply terminal for supplying a power supply voltage to the amplifier. The bypass capacitor section includes a first capacitor, a second capacitor, and a first switch circuit. The first capacitor includes a first end connected to a power supply path, and a second end. The second capacitor includes a first end connected to the second end of the first capacitor and a second end connected to ground. The first switch circuit includes a first terminal connected to the second end of the first capacitor and the first end of the second capacitor, and a second terminal connected to the ground. The first switch circuit switches between connection and non-connection between the second end of the first capacitor and the ground.
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Patent Agency Ranking
公开(公告)号：US20190190457A1
公开(公告)日：2019-06-20
申请号：US16220477
申请日：2018-12-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideyuki SATOU
Abstract: A power amplifier circuit includes a first transistor having a base supplied with an RF signal and a collector supplied with a variable power supply voltage corresponding to a level of the RF signal, the first transistor being configured to amplify the RF signal, a bias circuit including a second transistor that supplies a bias current to the base of the first transistor, and a bias adjustment circuit that decreases a current to be supplied from an emitter of the second transistor as the variable power supply voltage decreases, thereby decreasing the bias current to be supplied to the base of the first transistor.
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公开(公告)号：US20200304072A1
公开(公告)日：2020-09-24
申请号：US16823815
申请日：2020-03-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideyuki SATOU
Abstract: A power amplifying circuit includes a bias circuit that supplies a bias current or a bias voltage to a base of a first transistor, and at least one termination circuit that short-circuits a second-order harmonic of an amplified signal output from a collector of the first transistor to a ground voltage. An emitter of the first transistor is connected to ground. The bias circuit includes a second transistor. A collector of the second transistor is connected to the base of the first transistor. An emitter of the second transistor is connected to the emitter of the first transistor. A base of the second transistor is supplied with a predetermined voltage.
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公开(公告)号：US20190149095A1
公开(公告)日：2019-05-16
申请号：US16185394
申请日：2018-11-09
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideyuki SATOU
CPC classification number: H03F1/0216 , H03F1/0261 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/21 , H03F2200/451
Abstract: A power amplifier circuit includes a first transistor having a base to which a radio frequency (RF) signal is supplied and a collector to which a variable power-supply voltage corresponding to a level of the RF signal is supplied, and being configured to amplify the RF signal; a bias circuit including a second transistor configured to supply a bias current to the base of the first transistor; and an adjustment circuit configured to cause the bias current to be supplied to the base of the first transistor to decrease with decrease in the variable power-supply voltage by causing a current to be supplied to a base of the second transistor to decrease.
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公开(公告)号：US20210075369A1
公开(公告)日：2021-03-11
申请号：US17017184
申请日：2020-09-10
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yuri HONDA , Hisanori NAMIE , Hideyuki SATOU , Yoshiaki SUKEMORI
Abstract: A power amplifier circuit includes a first path and a second path between an input terminal and an output terminal, a first amplifier located in the first path operative in a first mode, a second amplifier located in the second path operative in a second mode, a first matching circuit between the first amplifier and the output terminal in the first path, a first capacitor having a first end connected to the output terminal side of the first matching circuit, and a second end, a first inductor having a first end connected to the second end of the first capacitor and a second end grounded, and a short-circuit switch connected in parallel with the first inductor. The short-circuit switch short-circuits the first and second ends of the first inductor in the first mode and is placed in an open-circuit position in the second mode.
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公开(公告)号：US20240146251A1
公开(公告)日：2024-05-02
申请号：US18495170
申请日：2023-10-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideyuki SATOU
CPC classification number: H03F1/0288 , H03F3/245 , H03F2200/06 , H03F2200/09 , H03F2200/451
Abstract: A differential Doherty amplifier circuit includes a first differential amplifier including a first carrier amplifier and a second carrier amplifier, a second differential amplifier including a first peak amplifier and a second peak amplifier, a first line connected to the first carrier amplifier and the first peak amplifier, and a second line connected to the second carrier amplifier and the second peak amplifier. The first differential amplifier and the second differential amplifier are formed on a die of a chip device parallel to an XY plane. The first line and the second line are each formed of a wiring line disposed in a substrate parallel to the XY plane. The chip device is flip-chip mounted on the substrate in a Z direction orthogonal to the XY plane.
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