Test apparatus and test method to a memory device

    公开(公告)号:US11598806B2

    公开(公告)日:2023-03-07

    申请号:US17155043

    申请日:2021-01-21

    IPC分类号: G01R31/317

    摘要: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.