公开(公告)号：US20190187213A1

公开(公告)日：2019-06-20

申请号：US15848177

申请日：2017-12-20

Applicant: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Shu-Hsien Wen ,  Kuo-Kuang Jen ,  Gwo-Huei You ,  Chung-Ling Tseng

IPC: G01R31/36 ,  H01M10/42 ,  H02J7/00 ,  H01M10/44

CPC classification number: G01R31/387 ,  G06F2217/78 ,  H01M10/4285 ,  H01M10/441 ,  H02J7/0006 ,  H02J7/0019 ,  H02J7/0021 ,  H02J7/0026 ,  H02J2007/005

Abstract: A battery balance management circuit includes an active and passive testing balance bus, a plurality of battery sets, a primary charging converter, a secondary charging system, an electrical load and a battery management system. An external balance management mechanism is utilized to compensate for current loss of the battery set, effectively enabling the battery sets to provide stable large current output.

公开(公告)号：US10444295B2

公开(公告)日：2019-10-15

申请号：US15848177

申请日：2017-12-20

Applicant: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Shu-Hsien Wen ,  Kuo-Kuang Jen ,  Gwo-Huei You ,  Chung-Ling Tseng

IPC: H02J7/00 ,  G01R31/387 ,  H01M10/42 ,  H01M10/44

Abstract: A battery balance management circuit includes an active and passive testing balance bus, a plurality of battery sets, a primary charging converter, a secondary charging system, an electrical load and a battery management system. An external balance management mechanism is utilized to compensate for current loss of the battery set, effectively enabling the battery sets to provide stable large current output.